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參數(shù)資料
| 型號： | 935229730557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁數(shù)： | 22/22頁 |
| 文件大?。?/td> | 162K |
| 代理商： | 935229730557 |
1999 Sep 16
9
Philips Semiconductors
Product specication
10-bit converter interface (ADC/DAC) for
quadrature transceiver
TDA8779H
STANDBY MODE OUTPUT DELAY TIMES; STDBYA; Tamb =25 °C
td(stb)LH
standby delay
(LOW-to-HIGH transition)
100
s
td(stb)HL
start-up delay
(HIGH-to-LOW transition)
100
s
CROSSTALK ON THE ADC
αct
crosstalk on the ADC
fCLK(DAC) = 16.384 MHz;
fCLK(ADC) = 8.192 MHz;
Tamb =25 °C; both DACs
switching between input
codes 0 and 1023; one
ADC 1 V (p-p) sine wave
at 4 MHz and the other
ADC set at the middle
code
50
55
dB
DAC part
DIGITAL INPUTS: D0D TO D9D AND CLKD
VIL
LOW-level input voltage
Tamb =25 °C0
0.8
V
VIH
HIGH-level input voltage
Tamb =25 °C
2.0
VCCD2
V
IIL
LOW-level input current
200
0
A
IIH
HIGH-level input current
10
+10
A
DIGITAL INPUT; STDBYD
VIL
LOW-level input voltage
Tamb =25 °C0
0.8
V
VIH
HIGH-level input voltage
Tamb =25 °C
2.0
VCCD2
V
IIL
LOW-level input current
10
+10
A
IIH
HIGH-level input current
10
+10
A
TIMING;Tamb =25 °C (see Fig.5)
fCLK(max)
maximum clock frequency
20
MHz
tCH
clock pulse width HIGH
20
ns
tCL
clock pulse width LOW
20
ns
tr
clock rise time
4
ns
tf
clock fall time
4
ns
ts
input data set-up time
11
ns
th
input data hold time
0
ns
ANALOG OUTPUTS; note 3
Vo(p-p)
output voltage
(peak-to-peak value)
full-scale
0.9
1
1.1
V
ZoL
output load impedance
see Fig.6
15
pF
0.3
k
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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