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參數(shù)資料
| 型號： | 935231710118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14 |
| 封裝： | 5.30 MM, PLASTIC, MO-150, SOT-337-1, SSOP-14 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 88K |
| 代理商： | 935231710118 |
2002 Mar 08
2
Philips Semiconductors
Product specication
Quad buffer/line driver with 5 Volt tolerant input/outputs;
3-state
74LVC125A
FEATURES
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard no. 8-1A
Specified from 40 to +85 °C and 40 to +125 °C.
DESCRIPTION
The 74LVC125A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V.
The 74LVC125A consists of four non-inverting buffers/line
drivers with 3-state outputs (nY) which are controlled by
the output enable input (nOE). A HIGH at nOE causes the
outputs to assume a high-impedance OFF-state.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay nA to nY
CL = 50 pF; VCC = 3.3 V
2.4
ns
CI
input capacitance
4.0
pF
CPD
power dissipation capacitance per gate
VCC = 3.3 V;
notes 1 and 2
12
pF
TYPE NUMBER
PACKAGES
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74LVC125AD
40 to +125 °C
14
SO
plastic
SOT108-1
74LVC125ADB
40 to +125 °C
14
SSOP
plastic
SOT337-1
74LVC125APW
40 to +125 °C
14
TSSOP
plastic
SOT402-1
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