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參數(shù)資料
| 型號： | 935231720112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 88K |
| 代理商： | 935231720112 |
2002 Mar 08
8
Philips Semiconductors
Product specication
Quad buffer/line driver with 5 Volt tolerant input/outputs;
3-state
74LVC125A
handbook, full pagewidth
MNA362
tPLZ
tPHZ
outputs
disabled
outputs
enabled
VY
VX
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE input
VI
VOL
VOH
VCC
VM
GND
tPZL
tPZH
VM
Fig.6 3-state enable and disable times.
VM = 1.5 V at VCC ≥ 2.7 V;
VM = 0.5VCC at VCC < 2.7 V;
VX =VOL + 0.3 V at VCC ≥ 2.7 V;
VX =VOL + 0.1 V at VCC < 2.7 V;
VY =VOH +0.3VatVCC ≥ 2.7 V;
VY =VOH +0.1VatVCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
handbook, full pagewidth
open
GND
50 pF
2
× VCC
VCC
VI
VO
MNA368
D.U.T.
CL
RT
RL
500
RL
500
PULSE
GENERATOR
S1
Fig.7 Load circuitry for switching times.
SWITCH POSITION
TEST
SWITCH
tPLH/tPHL
open
tPLZ/tPZL
2
× VCC
tPHZ/tPZH
GND
Definitions for test circuits:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VCC
VI
< 2.7 V
VCC
2.7 to 3.6 V
2.7 V
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