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參數(shù)資料
| 型號： | 935232710518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | PLASTIC, SOT-314, LQFP-64 |
| 文件頁數(shù)： | 36/75頁 |
| 文件大小： | 479K |
| 代理商： | 935232710518 |
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1998 May 15
41
Philips Semiconductors
Product specication
Enhanced Video Input Processor (EVIP)
SAA7111A
17 I2C-BUS DESCRIPTION
17.1
I2C-bus format
Table 7
Write procedure
Table 8
Read procedure (combined format)
Table 9
Description of I2C-bus format
Notes
1. If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed.
2. During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with
the I2C-bus specification).
3. The I2C-bus subaddress 00 has to be initialized with 0 before being read.
S
SLAVE ADDRESS W
ACK-s
SUBADDRESS
ACK-s
DATA (N BYTES)
ACK-s
P
S
SLAVE ADDRESS W
ACK-s
SUBADDRESS
ACK-s
Sr
SLAVE ADDRESS R
ACK-s
DATA (N BYTES)
ACK-m
P
CODE
DESCRIPTION
S
START condition
Sr
repeated START condition
Slave address W
0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH)
Slave address R
0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH)
ACK-s
acknowledge generated by the slave
ACK-m
acknowledge generated by the master
Subaddress
subaddress byte; see Table 10
Data
data byte; see Table 10; note 1
P
STOP condition
X = LSB slave
address
read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read
(the circuit is slave transmitter)
Slave address
read = 49H or 4BH; note 2
write = 48H or 4AH
IICSA = 0 or 1
Subaddresses
00H chip version
read and write; note 3
01H reserved
02h to 05H front-end part
read and write
06H to 13H decoder part
read and write
14H reserved
15H to 17H decoder part
read and write
18H to 19H reserved
1AH to 1CH Line-21 text slicer part
read only
1DH to 1EH reserved
1FH status byte
read only
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