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參數(shù)資料
| 型號(hào)： | 935235110512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48 |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 211K |
| 代理商： | 935235110512 |
9397 750 12871
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data sheet
Rev. 03 — 5 March 2004
2 of 17
Philips Semiconductors
74LVC16240A
16-bit buffer/line driver with 5 V tolerant inputs/outputs
3.
Quick reference data
[1]
CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = total load switching outputs;
Σ(C
L × VCC
2
× f
o) = sum of the outputs.
[2]
The condition is VI = GND to VCC.
4.
Ordering information
Table 1:
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tPHL, tPLH
propagation delay
nAn to nYn
CL =50pF;
VCC = 3.3 V
1.0
2.8
4.2
ns
tPZH, tPZL
3-state output enable
time nOE to nYn
CL =50pF;
VCC = 3.3 V
1.0
3.5
5.0
ns
tPHZ, tPLZ
3-state output disable
time nOE to nYn
CL =50pF;
VCC = 3.3 V
1.5
3.9
4.9
ns
CI
input capacitance
-
5.0
-
pF
CPD
power dissipation
capacitance per gate
VCC = 3.3 V
outputs enabled
-
12
-
pF
outputs disabled
-
4.0
-
pF
Table 2:
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVC16240ADGG
40 °C to +125 °C
TSSOP48
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
SOT362-1
74LVC16240ADL
40 °C to +125 °C
SSOP48
plastic shrink small outline package; 48 leads;
body width 7.5 mm
SOT370-1
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