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參數(shù)資料
| 型號： | 935235110518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 211K |
| 代理商： | 935235110518 |
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The 74LVC16240A is a high-performance, low power, low voltage, Si-gate CMOS device, superior to most advanced CMOS compatible
TTL families. Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices as a mixed 3.3 V and 5 V
environment.
The 74LVC16240A is a 16-bit inverting buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four
output enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state.
This device is fully specified for partial power-down applications using Ioff . The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is
powered down.
The 74LVC16240A is identical to the 74LVC16244A but has inverting outputs.
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground bounce
Direct interface with TTL levels
Complies with JEDEC standard no. 8-1 A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2 000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from -40 Cel to +85Cel and from -40 Cel to +125 Cel.
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(Product Specification)
v.3, 05-Mar-04, 17 Pages,
92kB
16-bit buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-
state
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16-bit buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state from NXP Semiconductors
22-Mar-2010
http://www.nxp.com/
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