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參數(shù)資料
| 型號： | 935235130112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, SOT-362-1, TSSOP2-48 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 150K |
| 代理商： | 935235130112 |
Philips Semiconductors
Product specification
74LVC16241A
16-bit buffer/line driver (3-State)
2
1997 Jul 29
853-2006 18217
FEATURES
5 volt tolerant inputs/outputs for interfacing with 5V logic
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum
noise and ground bounce
Direct interface with TTL levels
DESCRIPTION
The 74LVC16241A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families. Inputs can be driven from either 3.3V or 5V
devices. In 3-State operation, outputs can handle 5V. These
features allow the use of these devices in a mixed 3.3V/5V
environment.
The 74LVC16241A is a 16-bit buffer/line driver with 3-State outputs.
The 3-State outputs are controlled by the output enable inputs nOE
and nOE. Schmitt-trigger action at all inputs makes the circuit highly
tolerant for slower input rise and fall times. The device can be used
as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
1OE
1Y0
1Y1
GND
1Y2
1Y3
VCC
2Y1
GND
2Y2
2Y3
3Y0
3Y1
GND
2Y0
3Y2
3Y3
VCC
4Y0
4Y1
4A1
4A0
VCC
3A3
3A2
GND
3A1
3A0
2A3
2A2
GND
2A1
2A0
VCC
1A3
1A2
GND
1A1
1A0
2OE
21
22
23
24
25
26
27
28
GND
4Y2
4Y3
4OE
3OE
4A3
4A2
GND
SW00049
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 _C; tr = tf v 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
nAn to nYn
CL = 50pF
VCC = 3.3V
2.9
ns
CI
Input capacitance
5.0
pF
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
25
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in mW):
PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL x VCC2 x fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
48-Pin Plastic SSOP Type III
–40
°C to +85°C
74LVC16241A DL
VC16241A DL
SOT370-1
48-Pin Plastic TSSOP Type II
–40
°C to +85°C
74LVC16241A DGG
VC16241A DGG
SOT362-1
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