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參數(shù)資料
| 型號： | 935242080112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)器 |
| 英文描述： | HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 167K |
| 代理商： | 935242080112 |
December 1990
10
Philips Semiconductors
Product specication
14-stage binary ripple counter with oscillator
74HC/HCT4060
Notes
1. The value of additional quiescent supply current (
ICC) for a unit load of 1 is given here.
To determine
ICC per input, multiply this value by the unit load coefficient shown in the table below.
2. Only input MR (pin 12) has TTL input switching levels for the HCT versions.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr =tf = 6 ns; CL = 50 pF
INPUT
UNIT LOAD COEFFICIENT
MR
0.40
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
tPHL/ tPLH
propagation delay
RS to Q3
33
66
83
99
ns
4.5
Fig.12
tPHL/ tPLH
propagation delay
Qn to Qn+1
8
16
20
24
ns
4.5
Fig.14
tPHL
propagation delay
MR to Qn
21
44
55
66
ns
4.5
Fig.13
tTHL/ tTLH
output transition time
7
15
19
22
ns
4.5
Fig.12
tW
clock pulse width
RS; HIGH or LOW
16
6
20
24
ns
4.5
Fig.12
tW
master reset pulse
width MR; HIGH
16
6
20
24
ns
4.5
Fig.13
trem
removal time
MR to RS
26
13
33
39
ns
4.5
Fig.13
fmax
maximum clock pulse
frequency
30
80
24
20
MHz
4.5
Fig.12
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