參數(shù)資料
型號(hào)： 935244020112
廠商： NXP SEMICONDUCTORS
元件分類： 鎖存器
英文描述： ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
封裝： 7.50 MM, PLASTIC, SOT-163-1, SOL-20
文件頁(yè)數(shù)： 9/16頁(yè)
文件大小： 142K
代理商： 935244020112
Philips Semiconductors
Product specification
74ABT377A
Octal D-type flip-flop with enable
2
1997 Feb 26
853-1457 17800
FEATURES
Ideal for addressable register applications
8-bit positive edge-triggered register
Enable for address and data synchronization applications
Output capability: +64mA/-32mA
Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
Power-up reset
DESCRIPTION
The 74ABT377A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT377A has 8 edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered clock (CP)
input loads all flip-flops simultaneously when the Enable (E) input is
Low.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The E input must be stable one setup time prior to the Low-to-High
clock transition for predictable operation.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
Tamb = 25°C; GND = 0V
TYPICAL
UNIT
tPLH
tPHL
Propagation delay
CP to Qn
CL = 50pF; VCC = 5V
3.1
3.6
ns
CIN
Input capacitance
VI = 0V or VCC
4
pF
ICCH
Total current supply
Outputs High; VCC = 5.5V
500
nA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
20-Pin Plastic DIP
–40
°C to +85°C
74ABT377A N
SOT146-1
20-Pin plastic SO
–40
°C to +85°C
74ABT377A D
SOT163-1
20-Pin Plastic SSOP Type II
–40
°C to +85°C
74ABT377A DB
SOT339-1
20-Pin Plastic TSSOP Type I
–40
°C to +85°C
74ABT377A PW
74ABT377PWA DH
SOT360-1
PIN CONFIGURATION
20
19
18
17
16
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
E
SA00155
LOGIC SYMBOL
5
2
Q0
Q1
Q2
9
6
Q3
34
7
8
D0
D1
D2
D3
11
1
15
12
Q4
Q5
Q6
19
16
Q7
13
14
17
18
D4
D5
D6
D7
CP
OE
SA00152
相關(guān)PDF資料
PDF描述
935244030112 ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
935244160112 ABT SERIES, 20 1-BIT DRIVER, TRUE OUTPUT, PDSO56
935244170118 ABT SERIES, 20 1-BIT DRIVER, TRUE OUTPUT, PDSO56
935245480118 ALVT SERIES, 16 1-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO56
935245490118 ALVT SERIES, 16 1-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO56
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