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參數(shù)資料
| 型號： | 935244030112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | ABT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 |
| 封裝： | 5.30 MM, PLASTIC, SOT-339-1, SSOP-20 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 142K |
| 代理商： | 935244030112 |
Philips Semiconductors
Product specification
74ABT377A
Octal D-type flip-flop with enable
1997 Feb 26
6
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500
LIMITS
SYMBOL
PARAMETER
WAVEFORM
Tamb = +25oC
VCC = +5.0V
Tamb = -40 to +85oC
VCC = +5.0V +0.5V
UNIT
MIN
TYP
MIN
ts(H)
ts(L)
Setup time, High or Low
Dn to CP
2
1.5
0.7
0.5
1.5
ns
th(H)
th(L)
Hold time, High or Low
Dn to CP
2
1.0
–0.4
–0.6
1.0
ns
ts(H)
ts(L)
Setup time, High or Low
E to CP
2
2.0
1.1
1.0
2.0
ns
th(H)
th(L)
Hold time, High or Low
E to CP
2
1.0
–0.9
–0.1
1.0
ns
tw(H)
tw(L)
Clock Pulse width
High or Low
1
1.5
2.0
0.7
1.0
1.5
2.0
ns
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
VM
tPLH
tPHL
VM
CP
Qn
1/fMAX
tW(H)
tW(L)
SA00159
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width and Maximum Clock Frequency
CP
VM VM
VM
ts(L)
E
th(L)
th(H)
ts(H)
Dn
VM
ts
th
VM
SA00160
NOTE: The shaded areas indicate when the input is permitted to change for predict-
able output performance.
Waveform 2. Data and Enable Setup and Hold Times
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