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參數(shù)資料
| 型號： | 935245790118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門電路 |
| 英文描述： | HC/UH SERIES, 2-INPUT XOR GATE, PDSO5 |
| 封裝： | PLASTIC, SC-88A, 5 PIN |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 74K |
| 代理商： | 935245790118 |
92
XMEGA E5 [DATASHEET]
8153G–AVR–10/2013
Notes:
1.
Required only for fSCL > 100kHz.
2.
Cb = Capacitance of one bus line in pF.
3.
fPER = Peripheral clock frequency.
tLOW
Low period of SCL Clock
fSCL ≤ 100kHz
4.7
s
fSCL ≤ 400kHz
1.3
fSCL ≤ 1MHz
0.5
tHIGH
High period of SCL Clock
fSCL ≤ 100kHz
4
s
fSCL ≤ 400kHz
0.6
fSCL ≤ 1MHz
0.26
tSU;STA
Set-up time for a repeated START
condition
fSCL ≤ 100kHz
4.7
s
fSCL ≤ 400kHz
0.6
fSCL ≤ 1MHz
0.26
tHD;DAT
Data hold time
fSCL ≤ 100kHz
0
3.45
s
fSCL ≤ 400kHz
0
0.9
fSCL ≤ 1MHz
0
0.45
tSU;DAT
Data setup time
fSCL ≤ 100kHz
250
ns
fSCL ≤ 400kHz
100
fSCL ≤ 1MHz
50
tSU;STO
Setup time for STOP condition
fSCL ≤ 100kHz
4
s
fSCL ≤ 400kHz
0.6
fSCL ≤ 1MHz
0.26
tBUF
Bus free time between a STOP and
START condition
fSCL ≤ 100kHz
4.7
s
fSCL ≤ 400kHz
1.3
fSCL ≤ 1MHz
0.5
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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