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參數(shù)資料
| 型號： | 935247880551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 畫面疊加 |
| 英文描述： | PICTURE-IN-PICTURE IC, PQFP100 |
| 封裝： | PLASTIC, SOT-317-2, QFP-100 |
| 文件頁數(shù)： | 12/35頁 |
| 文件大小： | 273K |
| 代理商： | 935247880551 |
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1996 Aug 13
2
Philips Semiconductors
Preliminary specication
Picture-In-Picture (PIP) controller
SAB9076H
FEATURES
Display
Twin PIP in interlaced mode at 8-bit resolution
Sub-title mode features built in
Large display fine positioning area, both channels
independent
Only 2 Mbit required as external VDRAM
(2
× 1 Mbit or 1 × 2 Mbit)
Four 8-bit Analogue Digital Converters (ADCs; > 7-bit
performance) with clamp circuit
Most PIP modes handle interlaced pictures without joint
line error
Two PLLs which generate the line-locked clocks for the
acquisition channels
Display PLL to generate line-locked clock for the display
Three 8-bit Digital Analogue Converters (DACs)
4:1:1 data format
Data reduction factors 1 to 1, 1 to 2, 1 to 3 and 1 to 4,
horizontal and vertical independent.
I2C-bus programmable
Single and double PIP modes can be set
Full field still mode available
Several aspect ratios can be handled
Reduction factors can be set freely
Selection of vertical filtering type
Freeze of live pictures
Fine tuned display position, H (8-bit), V (8-bit),
both channels independent
Fine tuned acquisition area, H (4-bit), V (8-bit),
both channels independent
Eight main borders, sub-borders and background
colours selectable
Border and background brightness adjustable, 30%,
50%, 70% and 100% IRE
Several type of decoder input signals can be set.
GENERAL DESCRIPTION
The SAB9076H is a picture-in-picture controller for NTSC
TV-sets. The circuit contains ADCs, reduction circuitry,
memory control, display control and DACs.
The device inserts one or two live video signals with
original or reduced sizes into a live video signal. All video
signals are expected to be analog baseband signals.
The conversion into the digital environment and back to
the analog environment is carried out on chip. Internal
clocks are generated by two acquisition PLLs and a
display PLL.
Due to the two PIP channels and a large external memory
a wide range of PIP modes are offered. The emphasis is
put on single-PIP, double-PIP, split-screen mode and a
many multi-PIP modes.
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