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參數(shù)資料
| 型號(hào)： | 935250600118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, OCTAL 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013, SOT-137-1, SO-24 |
| 文件頁(yè)數(shù)： | 15/16頁(yè) |
| 文件大?。?/td> | 135K |
| 代理商： | 935250600118 |
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Philips Semiconductors
Product specification
74LVC646A
Octal bus transceiver/register (3-State)
2000 Jun 21
8
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3 V ± 0.3 V
VCC = 2.7 V
VCC =
1.2 V
UNIT
MIN
TYP1
MAX
MIN
MAX
TYP
tPHL/tPLH
Propagation delay
An, Bn to Bn, An
Figures 1, 6
1.5
3.9
6.8
1.5
7.8
15
ns
tPHL/tPLH
Propagation delay
CPAB, CPBA to Bn, An
Figures 2, 6
1.5
4.6
7.6
1.5
8.6
19
ns
tPHL/tPLH
Propagation delay
SAB, SBA to Bn, An
Figures 3, 6
1.5
4.9
8.5
1.5
9.5
19
ns
tPZH/tPZL
3-State output enable time
OEn to An, Bn
Figures 4, 6
1.5
4.5
7.8
1.5
8.8
20
ns
tPHZ/tPLZ
3-State output disable time
OEn to An, Bn
Figures 4, 6
1.5
3.9
6.1
1.5
7.1
10
ns
tPZH/tPZL
3-State output enable time
DIR to An, Bn
Figures 5, 6
1.5
4.6
7.9
1.5
8.9
20
ns
tPHZ/tPLZ
3-State output disable time
DIR to An, Bn
Figures 5, 6
1.5
3.5
6.0
1.5
7.0
12
ns
tW
Clock pulse width
HIGH or LOW
CPAB or CPBA
Figure 1, 3
3.3
1.9
–
3.3
–
ns
tsu
Set-up time
An, Bn to CPAB, CPBA
Figure 2
1.6
0.35
–
1.6
–
ns
th
Hold time
An, Bn to CPAB, CPBA
Figure 2
1.0
–0.3
–
1.0
–
ns
fmax
Maximum clock pulse frequency
Figure 2
150
250
–
125
–
ns
NOTE:
1. These typical values are at VCC = 3.3 V and Tamb = 25°C.
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