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參數(shù)資料
| 型號(hào)： | 935256880112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.25 A SWITCHING REGULATOR, 50 kHz SWITCHING FREQ-MAX, PDIP8 |
| 封裝： | SOT-97, DIP-8 |
| 文件頁數(shù)： | 21/22頁 |
| 文件大小： | 154K |
| 代理商： | 935256880112 |
1998 Aug 19
8
Philips Semiconductors
Preliminary specication
Greeny; GreenChip
TEA1501
Burst oscillator
The burst oscillator generates a triangular wave signal for
determination of the burst frequency. The burst frequency
is determined accurately and temperature independent by
the externally connected reference resistor RRef and burst
capacitor CBt.
Gate driver
The gate driver switches the power switch. The power
switch is turned on at the beginning of every oscillator
cycle and is turned off by the primary current comparator
or by the maximum on-time. The power switch is also
prevented from turning on if the Vaux voltage has reached
its regulation level or in case of active over temperature
protection or in case of active under voltage lockout
protection.
Power switch
The power switch is an integrated high voltage LDMOST
with a Rdson of 40 , a maximum peak drain voltage of
650 V
, a maximum continuous drain voltage of 500 V and
a maximum drain current of 0.25 A.
Primary current comparator
The primary current comparator senses the voltage across
the external sense resistor RSrc which reflects the primary
current. The detection level of the comparator is 0.5 V. The
power switch is switched off quickly when the source
voltage exceeds this detection level. The comparator has
a typical propagation delay of 80 ns. If the dV/dt of the
drain voltage has to be limited for EMI reasons, a capacitor
can be connected between the Drn and Src pins of
Greeny. The discharge current of this EMI capacitor does
not flow through the sense resistor RSrc and does not
activate the comparator.
Leading edge blanking
To prevent the power switch from switching off due to the
discharge current of the capacitance on the Drn pin a
Leading Edge Blanking (LEB) circuit has been
implemented. The leading edge blanking time is defined
as the maximum duration time needed to discharge the
capacitance at the drain of the power switch. The leading
edge blanking time is determined by the reference resistor
to obtain an accurate and temperature independent time.
The LEB time tracks with the period time of the switch
oscillator.
Modulator
The modulator determines the regulation level of the Vaux
voltage. For a burst duty cycle from 0 to 40% the Vaux
voltage is regulated to 20 V. For stable operation in burst
mode a decrease in regulation voltage is integrated for a
burst duty cycle above 40%. At 100% burst duty cycle the
regulation voltage is 17.5 V.
Counter
The power delivered to the load (auxiliary and secondary)
is a function of the number of energy pulses per burst,
according to the following formula:
Where
η is the efficiency, L
p is the primary inductance, Iprim
is the primary peak current, fburst is the burst frequency and
N is the number of pulses in one burst period.
The counter counts the number of pulses in each burst
period and detects if the Ndata threshold is passed. The
counter state is used for the data transfer function and for
the supply current tracking.
Fig.6 Regulation level VVaux versus burst duty cycle.
handbook, halfpage
MGM826
regulation
level Vaux
(V)
SVaux
17.5
20
0
40
CPVaux
burst duty cycle (%)
100
P
load
η
1
2
---
L
p
I
prim
2
f
burst
N
×
=
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