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參數(shù)資料
| 型號： | 935257900557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQCC84 |
| 封裝： | PLASTIC, SOT-189-2, LCC-84 |
| 文件頁數(shù)： | 9/42頁 |
| 文件大?。?/td> | 289K |
| 代理商： | 935257900557 |
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1996 Jul 08
17
Philips Semiconductors
Preliminary specication
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
Table 13 Subaddress 5E
Notes
1. Output black level/IRE = BLNNL
× 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal.
2. Output black level/IRE = BLNNL
× 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal.
Table 14 Subaddress 5F
Table 15 Subaddress 61:
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
BLNNL
variable blanking level
white-to-sync = 140 IRE(1)
BLNNL = 0
output blanking level = 17 IRE
BLNNL = 63 (3FH)
output blanking level = 42 IRE
white-to-sync = 143 IRE(2)
BLNNL = 0
output blanking level = 17 IRE
BLNNL = 63 (3FH)
output blanking level = 43 IRE
DECTYP
RTCI
logic 0
real time control input from SAA7151B
logic 1
real time control input from SAA7111
DATA BYTE
DESCRIPTION
BLNVB
variable blanking level during vertical blanking interval is typically identical to value of BLNNL
DATA BYTE
LOGIC LEVEL
DESCRIPTION
FISE
0
864 total pixel clocks per line; default after reset
1
858 total pixel clocks per line
PAL
0
NTSC encoding (non-alternating V component)
1
PAL encoding (alternating V component); default after reset
SCBW
0
enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4); wide clipping for
SECAM
1
standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4); default after reset
SECAM
0
no SECAM encoding; default after reset
1
SECAM encoding activated
YGS
0
luminance gain for white
black 100 IRE; default after reset
1
luminance gain for white
black 92.5 IRE including 7.5 IRE set-up of black
INPI
0
PAL switch phase is nominal; default after reset
1
PAL switch phase is inverted compared to nominal
DOWNA
0
DACs for CVBS, Y and C in normal operational mode; default after reset
1
DACs for CVBS, Y and C forced to lowest output voltage
DOWNB
0
DACs for R, G and B in normal operational mode; default after reset
1
DACs for R, G and B forced to lowest output voltage
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