1998 May 15
42
Philips Semiconductors
Product specication
Enhanced Video Input Processor (EVIP)
SAA7111A
Table 10 I2C-bus receiver/transmitter overview
Note
1. All unused control bits must be programmed with logic 0.
SLAVE ADDRESS
READ
WRITE
IICSA
49H
4BH
48H
4AH
0
1
REGISTER
FUNCTION
SUB-
ADDR
D7
D6
D5
D4
D3
D2
D1
D0
Chip version
00
ID07
ID06
ID05
ID04
ID03
ID02
ID01
ID00
Reserved
01
(1)
Analog input contr 1
02
FUSE1
FUSE0
GUDL2
GUDL1
GUDL0
MODE2
MODE1
MODE0
Analog input contr 2
03
(1)
HLNRS
VBSL
WPOFF
HOLDG
GAFIX
GAI28
GAI18
Analog input contr 3
04
GAI17
GAI16
GAI15
GAI14
GAI13
GAI12
GAI11
GAI10
Analog input contr 4
05
GAI27
GAI26
GAI25
GAI24
GAI23
GAI22
GAI21
GAI20
Horizontal sync start
06
HSB7
HSB6
HSB5
HSB4
HSB3
HSB2
HSB1
HSB0
Horizontal sync stop
07
HSS7
HSS6
HSS5
HSS4
HSS3
HSS2
HSS1
HSS0
Sync control
08
AUFD
FSEL
EXFIL
(1)
VTRC
HPLL
VNOI1
VNOI0
Luminance control
09
BYPS
PREF
BPSS1
BPSS0
VBLB
UPTCV
APER1
APER0
Luminance
brightness
0A
BRIG7
BRIG6
BRIG5
BRIG4
BRIG3
BRIG2
BRIG1
BRIG0
Luminance contrast
0B
CONT7
CONT6
CONT5
CONT4
CONT3
CONT2
CONT1
CONT0
Chroma saturation
0C
SATN7
SATN6
SATN5
SATN4
SATN3
SATN2
SATN1
SATN0
Chroma Hue control
0D
HUEC7
HUEC6
HUEC5
HUEC4
HUEC3
HUEC2
HUEC1
HUEC0
Chroma control
0E
CDTO
CSTD2
CSTD1
CSTD0
DCCF
FCTC
CHBW1
CHBW0
Reserved
0F
(1)
Format/delay control
10
OFTS1
OFTS0
HDEL1
HDEL0
VRLN
YDEL2
YDEL1
YDEL0
Output control 1
11
GPSW
CM99
FECO
COMPO
OEYC
OEHV
VIPB
COLO
Output control 2
12
RTSE1
RTSE0
TCLO
CBR
RGB888
DIT
AOSL1
AOSL0
Output control 3
13
VCTR1
VCTR0
CCTR1
CCTR0
BCHI1
BCHI0
BCLO1
BCLO0
Reserved
14
(1)
V_GATE1_START
15
VSTA7
VSTA6
VSTA5
VSTA4
VSTA3
VSTA2
VSTA1
VSTA0
V_GATE1_STOP
16
VSTO7
VSTO6
VSTO5
VSTO4
VSTO3
VSTO2
VSTO1
VSTO0
V_GATE1_MSB
17
(1)
VSTO8
VSTA8
Reserved
18-19
(1)
Text slicer status
1A
(1)
F2VAL
F2RDY
F1VAL
F1RDY
Decoded bytes of
the text slicer
1B
P1
BYTE16 BYTE15 BYTE14
BYTE13
BYTE12
BYTE11
BYTE10
1C
P2
BYTE26 BYTE25 BYTE24
BYTE23
BYTE22
BYTE21
BYTE20
Reserved
1D-1E
(1)
Status byte
1F
STTC
HLCK
FIDT
GLIMT
GLIMB
WIPA
SLTCA
CODE