參數(shù)資料
型號: 935260344112
廠商: NXP SEMICONDUCTORS
元件分類: 編、解碼器及復用、解復用
英文描述: ALVT SERIES, 12 MULTIPLEXER AND DEMUX/DECODER, PDSO56
封裝: 6.10 MM, PLASTIC, SOT-364-1, TSSOP2-56
文件頁數(shù): 7/17頁
文件大?。?/td> 182K
代理商: 935260344112
Philips Semiconductors - PIP - 74ALVT16260; 12-bit to 24-bit multiplexed D-type latches (3-State)
Product Information
74ALVT16260; 12-
bit to 24-bit
multiplexed D-type
latches (3-State)
Information as of 2003-04-22
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Download datasheet
topGeneral description
The 74ALVT16260 is a 12-bit to 24-bit multiplexed D-type latch used in applications where two separate data paths must
be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or
demultiplexing of address and data information in microprocessor or bus-interface applications. This device is alto useful in
memory-interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output enable
(OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank
control in the A to B direction.
Address and/or data information can be stored using the internal storage latches. The latch enable (LE1B, LE2B, LEA1B,
and LEA2B) inputs are used to control data storage. When the latch enable input is high, the latch is transparent. When the
latch enable input goes low, the data present at the inputs is latched and remains latched until the latch enable input is
returned high.
To ensure the high-impedance state during power-up or power-down, OE should be tied to Vcc through a pull-up resistor;
the minimum value of the resistor is determined by the current sinking capability of the driver.
The 74ALVT16260 is available in a 56-pin Shrink Small Outline Package (SSOP) and 56-pin Thin Shrink Small Outline
Package (TSSOP).
topFeatures
q
ESD protection exceeds 2000V per Mil-Std-883C, Method 3015; exceeds 200V using machine model
q
Latch-up protection exceeds 500mA per JEDEC Standard JESD-17.
q
Distributed Vcc and GND pin configuration minimizes high-speed switching noise.
q
Output capability (-32mA I OH , 64mA I OL ).
q
Bus hold inputs eliminate the need for external pull-up resistors.
q
5V I/O compatible
q
Live insertion/extraction permitted
q
Power-up 3-State
q
Power-up Reset
file:///G|/imaging/BITTING/CPL/20030424/042...03_9/PHGL/_HTML04232003/74ALVT16260DGG.html (1 of 3) [May-12-2003 12:40:08 PM]
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