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參數(shù)資料
| 型號： | 935260345112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | ALVT SERIES, 12 MULTIPLEXER AND DEMUX/DECODER, PDSO56 |
| 封裝： | 7.50 MM, PLASTIC, MO-118AB, SOT-371-1, SSOP3-56 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大小： | 182K |
| 代理商： | 935260345112 |
Philips Semiconductors
Product specification
74ALVT16260
2.5V/3.3V 12-bit to 24-bit multiplexed D-type latches
(3-State)
1998 Jan 30
10
AC WAVEFORMS
VM = 1.5V for all waveforms
The outputs are measured one at a time with one transition per measurement.
tw
VM
3V
0V
INPUT
SA00437
Figure 1. Pulse duration
VM
3V
0V
INPUT
tPLH
VM
VOH
VOL
tPHL
VOH
VOL
VM
tPHL
tPLH
OUTPUT
SA00438
All input pulses are supplied by generators having the following
characteristics: PRR
≤ 10MHz, ZO = 50, tr ≤ 2.5ns, tf ≤ 2.5ns.
Figure 2. Propagation delay times;
inverting and non-inverting outputs
VM
3V
0V
DATA INPUT
0V
3V
TIMING INPUT
VM
tsu
th
SA00439
Figure 3. Setup and hold times
VM
3V
0V
OUTPUT
CONTROL
tPZL
VM
VOL + 0.3V
3.5V
VOL
tPLZ
VOH
≈0V
VOH – 0.3V
tPZH
tPHZ
OUTPUT
WAVEFORM 1
S1 AT 7V
VM
OUTPUT
WAVEFORM 2
S1 AT OPEN
SA00440
Waveform 1 is for an output with internal conditions such that the
output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the
output is high except when disabled by the output control.
Figure 4. Enable and disable times;
low- and high-level enabling
TEST LOAD CIRCUIT
CL = 50pF
(INCLUDES PROBE AND
JIG CAPACITANCE)
500
500
FROM OUTPUT UNDER TEST
S1
7V
OPEN
GND
Load Circuit for Outputs
TEST
S1
tPLH/tPHL
Open
tPLZ/tPZL
7V
tPHZ/tPZH
Open
SA00441
Figure 5. Test load circuit
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