參數(shù)資料
型號: 935260698551
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP160
封裝: PLASTIC, SOT-322, QFP-160
文件頁數(shù): 7/148頁
文件大?。?/td> 692K
代理商: 935260698551
1998 Apr 09
104
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Fig.32 Intel style block transfer without address increment.
handbook, full pagewidth
MHB064
address phase
tdsw
taz
tmin
address
write data
read data
second data phase
first data phase
tah
tas
tdhr
tdsrd
tdsrh
tdhw
trwi
trdy
AD(WR)
AD(RD)
SBHE
ALE
RDN
WRN
RDY
7.15.4.2
Target bus cycle in Motorola mode
The target transfer cycle starts with applying the target
address onto the multiplexed address/data lines. By
setting the Address Strobe (AS) to LOW it is indicated that
the direction signal RWN (Read/Write Not) and the
address are valid. The AS signal is usable as a address
latch enable signal. After asserting AS LOW the
address/data lines will change to the data transfer state.
The indication of valid data in write mode or the request for
data in read mode is done by transition of Upper Data
Strobe (UDS) and/or Lower Data Strobe (LDS) to LOW.
Since the selection of the upper and lower bytes for
transfer is done via LDS/UDS there is no need for
decoding address line A0. Only AD15 to AD1 are needed
for transmitting the (word-)address. Slaves with
handshake ability have to drive DTACK LOW when they
have placed valid data onto AD16 in read mode or when
they have read their data in write mode. The cycle is ended
when a TIMEOUT condition at inactive DTACK or a
positive DTACK edge is detected. Then AS, LDS, UDS
and RWN are reset to HIGH. A new cycle will not start
before detection of resetting DTACK to HIGH.
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