參數(shù)資料
型號(hào)： 935260736118
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 鎖存器
英文描述： LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝： 4.40 MM, PLASTIC, MO-153, SOT-402-1, TSSOP-14
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 99K
代理商： 935260736118
2002 Jun 18
2
Philips Semiconductors
Product specication
Dual D-type ip-op with set and reset; positive-edge
trigger
74LVC74A
FEATURES
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard no. 8-1A
Specified from 40 to +85 °C and 40 to +125 °C.
DESCRIPTION
The 74LVC74A is a high-performance, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74LVC74A is a dual positive edge triggered D-type
flip-flop with individual data (D) inputs, clock (CP) inputs,
set (SD) and (RD) inputs, and complementary Q and Q
outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition, for predictable operation.
Schmitt-trigger action at all inputs makes the circuit highly
tolerant to slower input rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay
nCP to nQ, nQCL = 50 pF; VCC = 3.3 V
2.5
ns
nSD to nQ, nQCL = 50 pF; VCC = 3.3 V
2.5
ns
nRD to nQ, nQCL = 50 pF; VCC = 3.3 V
2.5
ns
fmax
maximum clock frequency
CL = 50 pF; VCC = 3.3 V
250
MHz
CI
input capacitance
4.0
pF
CPD
power dissipation capacitance per gate
VCC = 3.3 V; notes 1 and 2
15
pF
相關(guān)PDF資料
PDF描述
935260734118 LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
935260742118 LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14
935260740112 LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14
935260741118 LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14
935260740118 LVC/LCX/Z SERIES, HEX 1-INPUT INVERT GATE, PDSO14
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