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參數(shù)資料
| 型號(hào)： | 935260938557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, SOT-205, QFP-44 |
| 文件頁數(shù)： | 5/26頁 |
| 文件大小： | 197K |
| 代理商： | 935260938557 |
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1998 Feb 05
13
Philips Semiconductors
Objective specication
Multimedia video data acquisition circuit
SAA5284
Fig.4 Intel mode interface write cycle timing.
handbook, full pagewidth
MGK146
D7 to D0
A2 to A0
WR
RDY
CS0 or CS1
t1
t5
t6
t3
t2
t4
t0
B(2)
A(1)
t7
valid address
valid data
(1) Event A occurs when WR + CS0 + CS1 = 0 (boolean).
(2) Event B occurs when WR + CS0 + CS1 = 1 (boolean).
Table 4
Intel-mode interface write cycle timing (12 MHz clock)
Note
1. Legacy AT bus PCs may not satisfy this requirement as they are not ISA compatible. An application fix is available
in the
“SAA5284 Users Guide”.
SYMBOL
DESCRIPTION
MIN.
MAX.
UNIT
t0
minimum cycle time
333
833
ns
t1
address set-up time
0
ns
t2
address hold time
0
ns
t3
data set-up time, note 1
0
ns
t4
data hold time
0
ns
t5
RDY set-up time
83
170
ns
t6
RDY LOW time
83
530
ns
t7
event B to next event A time
83
ns
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