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參數(shù)資料
| 型號(hào)： | 935261122118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SOT-341-1, SSOP-28 |
| 文件頁(yè)數(shù)： | 28/29頁(yè) |
| 文件大?。?/td> | 241K |
| 代理商： | 935261122118 |
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1999 Jan 06
8
Philips Semiconductors
Product specication
10-bit high-speed low-power ADC
TDA8763A
Rlad
resistor ladder
245
TCRlad
temperature coefcient of the
resistor ladder
1860
ppm
456
m
/K
Voffset(B)
offset voltage BOTTOM
VRT VRB = 2.37 V; note 2
175
mV
Voffset(T)
offset voltage TOP
VRT VRB = 2.37 V; note 2
175
mV
Vi(p-p)
analog input voltage
(peak-to-peak value)
note 3
1.70
2.02
2.55
V
Outputs
DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND)
VOL
LOW-level output voltage
IOL = 1 mA
0
0.5
V
VOH
HIGH-level output voltage
IOH = 1mA
VCCO 0.5
VCCO
V
IOZ
output current in 3-state mode
0.5 V < Vo <VCCO
20
+20
A
Switching characteristics
CLOCK INPUT CLK; see Fig.4; note 1
fclk(max)
maximum clock frequency
TDA8763AM/3
30
MHz
TDA8763AM/4
40
MHz
TDA8763AM/5
50
MHz
tCPH
clock pulse width HIGH
full effective bandwidth
8.5
ns
tCPL
clock pulse width LOW
full effective bandwidth
5.5
ns
Analog signal processing
LINEARITY
INL
integral non-linearity
fclk = 40 MHz; ramp input
±0.8
±2.0
LSB
DNL
differential non-linearity
fclk = 40 MHz; ramp input
±0.5
±0.9
LSB
Eoffset
offset error
middle code; VRB = 1.3 V;
VRT = 3.67 V
±1
LSB
EG
gain error (from device to
device) using external
reference voltage
VRB = 1.3 V; VRT = 3.67 V;
note 4
±0.1
%
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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