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參數(shù)資料
| 型號： | 935261242112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 20-BIT DAC, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 142K |
| 代理商： | 935261242112 |
2000 Jan 10
10
Philips Semiconductors
Preliminary specication
Low-cost stereo lter DAC
UDA1320ATS
Table 5
Data transfer of type ‘status’
Table 6
Data transfer of type ‘data’
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REGISTER SELECTED
0
SC1
SC0
IF2
IF1
IF0
0
System Clock frequency (1 : 0);
data Input Format (2 : 0)
10000000
reserved
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
REGISTER SELECTED
0
VC5
VC4
VC3
VC2
VC1
VC0
Volume Control (5 : 0)
01000000
reserved
1
0
DE1
DE0
MT
0
DE-emphasis (1 : 0); MuTe
11000001
default setting
9.3
Programming the features
When the data transfer of type ‘STATUS’ is selected, the
features SYSTEM CLOCK FREQUENCY and DATA
INPUT FORMAT can be controlled.
System clock frequency: a 2-bit value to select the used
external clock frequency.
Table 7
System clock settings
Data input format: a 3-bit value to select the data format.
Table 8
Data input format settings
When the data transfer of type ‘DATA’ is selected, the
features VOLUME, DE-EMPHASIS and MUTE can be
controlled.
Volume control: a 6-bit value to program the volume
attenuation (VC5 to VC0), 0 to
∞ dB in steps of 1 dB.
Table 9
Volume settings
De-emphasis: a 2-bit value to enable the digital
de-emphasis filter.
Table 10 De-emphasis settings
Mute: a 1-bit value to enable the digital mute.
Table 11 Mute setting
SC1
SC0
FUNCTION
0
512fs
0
1
384fs
1
0
256fs
1
not used
IF2
IF1
IF0
FUNCTION
000
I2Sbus
0
1
LSB-justied, 16 bits
0
1
0
LSB -justied, 18 bits
0
1
LSB-justied, 20 bits
1
0
MSB-justied
1
0
1
not used
1
0
not used
1
not used
VC5
VC4
VC3
VC2
VC1
VC0
VOLUME (dB)
000000
0
000001
0
000010
1
000011
2
::::::
:
111101
60
111111
∞
DE1
DE0
FUNCTION
0
no de-emphasis
0
1
de-emphasis, 32 kHz
1
0
de-emphasis, 44.1 kHz
1
de-emphasis, 48 kHz
MT
FUNCTION
0
no muting
1
muting
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