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參數(shù)資料
| 型號(hào)： | 935261327518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | DUAL 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP64 |
| 封裝： | PLASTIC, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 6/26頁 |
| 文件大小： | 262K |
| 代理商： | 935261327518 |
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1999 Sep 16
14
Philips Semiconductors
Objective specication
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
Note
1. Single-ended clock signal sources are allowed. The unused clock input is internally biased at the logical threshold
(1.65 V for nominal supply conditions), and should be correctly decoupled.
COMMON MODE REFERENCE OUTPUTS (V
OREF
1 AND VOREF2)
Vo(ref)
reference output voltage
VDDA 0.42 V
V
Ro(ref)
reference output resistance
at Vo(cm)(ref)
400
Io(ref)
reference maximum output
current
at Vo(cm)(ref) 0.2 V
170
A
Co(ref)
reference output capacitance
3pF
Serial Interface
DIGITAL INPUTS (SEN1, SEN2, SCLK, SDATA AND SMODE)
VIL
LOW-level input voltage
0
0.8
V
VIH
HIGH-level input voltage
2.0
VDDD
V
IIH
HIGH-level input current
50
+5
A
IIL
LOW-level input current
50
+5
A
GAIN CONTROL DATA TIMING (see Fig.4)
fSCLK(max)
maximum clock frequency
5
MHz
tW(SCLKH)
clock pulse width HIGH
20
ns
tW(SCLKL)
clock pulse width LOW
20
ns
tsu(SEN-SCLK)
SEN to SCLK set-up time
5
ns
th(SEN-SCLK)
SEN to SCLK hold time
5
ns
tsu(SDATA-SCLK) SDATA to SCLK set-up time
5
ns
th(SMODE-SCLK) SMODE to SCLK hold time
5
ns
th(SMODE-SEN)
SMODE to SEN hold time
5
ns
td(SEN-Q)
delay SEN rising edge to
change gain control register
value
5ns
td(SCLK-Q)
delay SCLK rising edge to
change gain control register
value
5ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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