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參數(shù)資料
| 型號： | 935261327557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | DUAL 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP64 |
| 封裝： | PLASTIC, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 5/26頁 |
| 文件大?。?/td> | 262K |
| 代理商： | 935261327557 |
1999 Sep 16
13
Philips Semiconductors
Objective specication
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
DIGITAL OUTPUTS (A0 TO A7 AND B0 TO B7)
VOL
LOW-level output voltage
IO =1mA
0.4
V
VOH
HIGH-level output voltage
IO = 1mA
VDDO 0.4 V
V
IOZ
output current in 3-state mode VO > 0.4 V;
VO <(VDDO 0.4 V)
20
+20
A
ADC CLOCK TIMING
fCLK(max)
maximum clock frequency
100
MHz
tW(CLKL)
clock pulse width LOW
duration
4.0
ns
tW(CLKH)
clock pulse width HIGH
duration
4.0
ns
tr(CLK)
clock pulse rise time
0.75
1
2
ns
tf(CLK)
clock pulse fall time
0.75
1
2
ns
DATA TIMING (see Fig.4); FCLK = 100 MHZ;CDPGAC =10 PF
td(s)(D)
data sampling delay time
tbf
ns
td(Q)
data output delay time
SR HIGH
5.0
tbf
ns
SR LOW
tbf
ns
th(Q)
data output hold time
SR HIGH
tbf
5.0
ns
SR LOW
tbf
ns
3-STATE OUTPUT DELAY TIMES (see Fig.6)
tdZH
output delay enable at logic
HIGH
SR HIGH
tbf
ns
SR LOW
tbf
ns
tdZL
output delay enable at logic
LOW
SR HIGH
tbf
ns
SR LOW
tbf
ns
tdHZ
output delay disable at logic
HIGH
SR HIGH
tbf
ns
SR LOW
tbf
ns
tdLZ
output delay disable at logic
LOW
SR HIGH
tbf
ns
SR LOW
tbf
ns
ADC REFERENCE OUTPUTS (V
REF
1 AND VREF2)
Vo(ref)
ADC reference output voltage
1.24
V
Ro(ref)
ADC reference output
resistance
at Vo(ref)
10
Io(ref)(max)
ADC reference maximum
output current
4.0
mA
Co(ref)
ADC reference output
capacitance
3pF
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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