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參數(shù)資料
| 型號： | 935261537118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | DELTA-SIGMA ADC, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-152, SOT-369-1, SSOP-16 |
| 文件頁數(shù)： | 17/18頁 |
| 文件大?。?/td> | 152K |
| 代理商： | 935261537118 |
2000 Feb 08
8
Philips Semiconductors
Preliminary specication
Low-voltage low-power stereo audio ADC
UDA1360TS
AC CHARACTERISTICS (ANALOG)
VDDD =VDDA =3V; fi = 1 kHz; Tamb =25 °C; all voltages referenced to ground (pins 10 and 15);
unless otherwise specied.
AC CHARACTERISTICS (DIGITAL)
VDDD =VDDA = 2.7 to 3.6 V; Tamb = 20 to +85 °C; all voltages referenced to ground (pins 10 and 15);
unless otherwise specied.
SYMBOL
PARAMETER
CONDITIONS
TYP.
MAX.
UNIT
Vi(rms)
input voltage (RMS value)
see Table 1
1.0
V
i
unbalance between channels
0.1
dB
(THD + N)/S
total harmonic distortion plus
noise-to-signal ratio
at 0 dB
85
80
dB
at
60 dB; A-weighted
37
33
dB
S/N
signal-to-noise ratio
VI = 0 V; A-weighted
97
dB
α
cs
channel separation
100
dB
PSRR
power supply rejection ratio
30
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Timing
Tsys
clock cycle
fsys = 256fs
71
89
782
ns
fsys = 384fs
47
59
522
ns
tCWL
fsys LOW-level pulse width
0.4Tsys
0.6Tsys
ns
tCWH
fsys HIGH-level pulse width
0.4Tsys
0.6Tsys
ns
Serial data timing (see Fig.3)
Tcy
bit clock cycle
1
64fs
ns
tBCK(H)
bit clock HIGH time
100
ns
tBCK(L)
bit clock LOW time
100
ns
tr
rise time
20
ns
tf
fall time
20
ns
td;DAT
data output delay time (from BCK
falling edge)
80
ns
td;DAT(WS)
data output delay time (from WS
edge)
MSB-justied format
80
ns
th;DAT
data output hold time
0
ns
ts;WS
word selection set-up time
20
ns
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