參數(shù)資料
型號： 935261770512
廠商： NXP SEMICONDUCTORS
元件分類： ADC
英文描述： 1-CH 9-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
封裝： PLASTIC, SOT-341-1, SSOP-28
文件頁數(shù)： 25/27頁
文件大小： 218K
代理商： 935261770512
1998 Nov 03
7
Philips Semiconductors
Product specication
9-bit analog-to-digital converter
for digital video
TDA8761A
Reference voltages for the resistor ladder; see Table 1
VRB
reference voltage BOTTOM
1.2
1.3
2.45
V
VRT
reference voltage TOP
3.2
3.43
VCCA 0.8 V
Vdiff
differential reference voltage
VRT VRB
2
2.13
3.0
V
Iref
reference current
VRT VRB = 2.13 V
8.7
mA
RLAD
resistor ladder
245
TCRLAD
temperature coefcient of the
resistor ladder
1860
ppm
456
m
/K
VosB
offset voltage BOTTOM
note 2
160
mV
VosT
offset voltage TOP
note 2
160
mV
Vi(p-p)
analog input voltage
(peak-to-peak value)
note 3
1.7
1.81
2.55
V
Outputs
DIGITAL OUTPUTS D8 TO D0 AND IR (REFERENCED TO OGND)
VOL
LOW-level output voltage
IOL = 1 mA
0
0.5
V
VOH
HIGH-level output voltage
IOH = 1mA
VCCO 0.5
VCCO
V
IOZ
output current in 3-state mode
0.5V<VO <VCCO
20
+20
A
Switching characteristics
CLOCK INPUT CLK; see Fig.4; note 1
fclk(max)
maximum clock frequency
40
MHz
tCPH
clock pulse width HIGH
10
ns
tCPL
clock pulse width LOW
10
ns
Analog signal processing
LINEARITY
INL
integral non-linearity
fclk = 30 MHz; ramp input ±0.4
±1
LSB
AINL
AC integral non-linearity
full-scale input sine
wave; note 4
±0.75
±0.9
LSB
50% full-scale input sine
wave; note 4
±0.5
±0.75
LSB
DNL
differential non-linearity
fclk = 30 MHz; ramp input ±0.3
±0.7
LSB
ADNL
AC differential non-linearity
full-scale input sine
wave; note 4
±0.5
±0.75
LSB
50% full-scale input sine
wave; note 4
±0.3
±0.5
LSB
OFER
offset error
middle code;
VRB = 1.3 V;
VRT = 3.43 V
±1
LSB
GER
gain error (from
device to device)
VRB = 1.3 V;
VRT = 3.43 V; note 5
±0.1
%
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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