參數(shù)資料
型號(hào)： 935261790118
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝： 5.30 MM, PLASTIC, SSOP-28
文件頁數(shù)： 11/31頁
文件大?。?/td> 199K
代理商： 935261790118
2000 Feb 04
19
Philips Semiconductors
Preliminary specication
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1344TS
TIMING
VDDD =VDDA =VDDO = 2.7 to 3.6 V; Tamb = 40 to +85 °C; RL =5k; all voltages referenced to ground; unless
otherwise specied.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock input (see Fig.7)
Tsys
system clock cycle time
fsys = 256fs
78
88
262
ns
fsys = 384fs
52
59
174
ns
fsys = 512fs
39
44
132
ns
tCWH
system clock HIGH time
fsys < 19.2 MHz
0.30Tsys
0.70Tsys ns
fsys ≥ 19.2 MHz
0.40Tsys
0.60Tsys ns
tCWL
system clock LOW time
fsys < 19.2 MHz
0.30Tsys
0.70Tsys ns
fsys ≥ 19.2 MHz
0.40Tsys
0.60Tsys ns
Serial interface input/output data (see Fig.8)
fBCK
bit clock frequency
64fs
Hz
Tcy(BCK)
bit clock cycle time
Tcy(s) = cycle time of
sample frequency
ns
tBCKH
bit clock HIGH time
100
ns
tBCKL
bit clock LOW time
100
ns
tr
rise time
20
ns
tf
fall time
20
ns
tsu(WS)
word select set-up time
20
ns
th(WS)
word select hold time
10
ns
tsu(DATAI)
data input set-up time
20
ns
th(DATAI)
data input hold time
0
ns
th(DATAO)
data output hold time
0
ns
td(DATAOBCK) data output to bit clock delay
from BCK falling edge
80
ns
td(DATAOWS) data output to word select delay
from WS edge for
MSB-justied format
80
ns
L3 interface input (see Figs 4 and 5)
Tcy(CLK)L3
L3CLOCK cycle time
500
ns
tCLK(L3)H
L3CLOCK HIGH time
250
ns
tCLK(L3)L
L3CLOCK LOW time
250
ns
tsu(L3)A
L3MODE set-up time for address mode
190
ns
th(L3)A
L3MODE hold time for address mode
190
ns
tsu(L3)D
L3MODE set-up time for data transfer
mode
190
ns
th(L3)D
L3MODE hold time for data transfer mode
190
ns
tstp(L3)
L3MODE stop time
190
ns
tsu(L3)DA
L3DATA set-up time in data transfer and
address mode
190
ns
th(L3)DA
L3DATA hold time in data transfer and
address mode
30
ns
T
cy(s)
64
-------------
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