參數(shù)資料
型號： 935262104026
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, UUC28
封裝： DIE IN WAFFLE CARRIER-28
文件頁數(shù)： 32/34頁
文件大?。?/td> 250K
代理商： 935262104026
Philips Semiconductors
Product specification
SCC2692
Dual asynchronous receiver/transmitter (DUART)
1998 Sep 04
7
AC CHARACTERISTICS (Continued)1, 2, 4
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
Min
Typ3
Max
UNIT
Port Timing5 (See Figure 5)
tPS
Port input setup time before RDN Low
0
ns
tPH
Port input hold time after RDN High
0
ns
tPD
OPn output valid from WRN High
400
ns
Interrupt Timing (See Figure 6)
9
INTRN (or OP3-OP7 when used as interrupts) negated from:
9
Read RHR (RxRDY/FFULL interrupt)
300
ns
9
Write THR (TxRDY interrupt)
300
ns
tIR9
Reset command (break change interrupt)
300
ns
Stop C/T command (counter interrupt)
300
ns
Read IPCR (input port change interrupt)
300
ns
Write IMR (clear of interrupt mask bit)
300
ns
Clock Timing (See Figure 7)
tCLK
X1/CLK High or Low time
100
ns
fCLK10
X1/CLK frequency
0
3.6864
4
MHz
tCTC
CTCLK (IP2) High or Low time
100
ns
fCTC8
CTCLK (IP2) frequency
0
4
MHz
tRX
RxC High or Low time
220
ns
fRX8
RxC frequency
(16X)
0
2
MHz
(1X)
0
1
MHz
tTX
TxC High or Low time
220
ns
fTX8
TxC frequency
(16X)
0
1
MHz
(1X)
0
1
MHz
Transmitter Timing (See Figure 8)
tTXD
TxD output delay from TxC external clock input on IP pin
350
ns
tTCS
Output delay from TxC low at OP pin to TxD data output
0
150
ns
Receiver Timing (See Figure 9)
tRXS
RxD data setup time before RxC high at external clock input on IP pin
240
ns
tRXH
RxD data hold time after RxC high at external clock input on IP pin
200
ns
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
3. Typical values are at +25
°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: CL = 150pF, except interrupt outputs. Test conditions for interrupt outputs: CL = 50pF, RL = 2.7K to VCC.
5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN
and RDN (also CEN and WRN) are ORed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for tRWD to guarantee that any status register changes are valid.
7. Guaranteed by characterization of sample units.
8. Minimum frequencies are not tested but are guaranteed by design.
9. 325ns maximum for TA > 70°C.
10. Operation to 0MHz is assured by design. Minimum test frequency is 2.0MHz. Crystal frequencies 2 to 4 MHz.
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