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參數(shù)資料
| 型號： | 935262254557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | PLASTIC, SOT-317-2, QFP-64 |
| 文件頁數(shù)： | 13/40頁 |
| 文件大?。?/td> | 250K |
| 代理商： | 935262254557 |
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1999 Feb 24
20
Philips Semiconductors
Product specication
Triple high-speed Analog-to-Digital
Converter (ADC)
TDA8752A
Table 8
Phase registers bits
The default programmed value is as follows:
No external clock: CKA at logic 0
No use of the second clock: CKB at logic 0
Phase shift for CKAO and CKADCO = 0°
Phase shift for CKBO = 0°.
I2C-bus protocol
Table 9
I2C-bus address
The I2C-bus address of the circuit is 10011 xx0.
Bits A2 and A1 are fixed by the potential on pins ADD1 and ADD2. Thus, four TDA8752As can be used on the same
system, using the addresses for ADD1 and ADD2 with the I2C-bus. The A0 bit must always be equal to logic 0 because
it is not possible to read the data in the register. The timing and protocol for the I2C-bus are standard. Two sequences
are available, see Tables 10 and 11.
Table 10 Address sequence for mode 0; note 1
Note
1. Where: S = START condition, ACK = acknowledge and P = STOP condition.
Table 11 Address sequence for mode 1; note 1
Note
1. Where: S = START condition, ACK = acknowledge and P = STOP condition.
Pa4 AND Pb4
Pa3 AND Pb3
Pa2 AND Pb2
Pa1 AND Pb1
Pa0 AND Pb0
PHASE SHIFT (
°)
000000
00001
11.25
↓↓↓↓↓↓
11110
337.5
11111
348.75
A7
A6
A5
A4
A3
A2
A1
A0
10011
ADD2
ADD1
0
S
IC ADDRESS
ACK
SUBADDRESS
REGISTER1
ACK
DATA
REGISTER1
(see Table 1)
ACK
SUBADDRESS
REGISTER2
ACK
to
P
S
IC ADDRESS
ACK
SUBADDRESS
xxx1 1111
ACK
DATA
REGISTER1
(see Table 1)
ACK
DATA
REGISTER2
ACK
to
P
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