1999 May 31
13
Philips Semiconductors
Product specication
Digital video encoder
SAA7126H; SAA7127H
Table 8
Subaddress 29H
Table 9
Subaddresses 2AH to 2CH
Table 10 Subaddress 2DH
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
REMARKS
BE
ending point of burst in clock cycles
PAL: BE = 29 (1DH); default after reset
NTSC: BE = 29 (1DH)
SRES
0
pin 19 is Real-Time Control Input (RTCI)
1
pin 19 is Sync Reset input (SRES)
a HIGH impulse resets synchronization of the
encoder (rst eld, rst line)
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
CG
LSB of the respective bytes are encoded immediately after run-in, the MSBs of the
respective bytes have to carry the CRCC bits, in accordance with the denition of copy
generation management system encoding format.
CGEN
0
copy generation data output is disabled; default after reset
1
copy generation data output is enabled
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
BTRI
0
DAC for BLUE output in 3-state mode (high-impedance)
1
DAC for BLUE output in normal operation mode; default after reset
GTRI
0
DAC for GREEN output in 3-state mode (high-impedance)
1
DAC for GREEN output in normal operation mode; default after reset
RTRI
0
DAC for RED output in 3-state mode (high-impedance)
1
DAC for RED output in normal operation mode; default after reset
CVBSTRI
0
DAC for CVBS output in 3-state mode (high-impedance)
1
DAC for CVBS output in normal operation mode; default after reset
CEN
0
RED output signal is switched to R DAC; default after reset
1
chrominance output signal is switched to R DAC
CVBSEN
0
BLUE output signal is switched to B DAC; default after reset
1
CVBS output signal is switched to B DAC
VBSEN0
0
if CSYNC = 0, CVBS output signal is switched to CVBS DAC; default after reset
1
if CSYNC = 0, luminance (VBS) output signal is switched to CVBS DAC
VBSEN1
0
GREEN output signal is switched to G DAC; default after reset
1
luminance (VBS) output signal is switched to G DAC