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參數(shù)資料
| 型號： | 935262383518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 30 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 15/55頁 |
| 文件大?。?/td> | 318K |
| 代理商： | 935262383518 |
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Philips Semiconductors
Preliminary specification
XA-S3
XA 16-bit microcontroller
32K/1K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
2000 Mar 09
22
CMOD Address = 490H
Reset Value = 00H
CIDL
WDTE
–
CPS1
CPS0
ECF
Bit:
Symbol
Function
CIDL
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
WDTE
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
–
Not implemented, reserved for future use.*
CPS1
PCA Count Pulse Select bit 1.
CPS0
PCA Count Pulse Select bit 0.
CPS1
CPS0
PCA Timer Count Source
0
X
TClk (Osc/4, Osc/16, or Osc/64)
1
0
Timer 0 overflow
1
ECI (PCA External Clock Input (max rate = Osc/4)
ECF
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
NOTE:
*
User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. In that case, the reset or inactive value of the new bit will be
0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** fOSC = oscillator frequency
SU01306
7
6
5
432
1
0
Figure 10. CMOD: PCA Counter Mode Register
CCON Address = 41AH
Reset Value = 00H
CF
CR
–
CCF4
CCF3
CCF2
CCF1
CCF0
Bit Addressable
Bit:
Symbol
Function
CF
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
CR
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
–
Not implemented, reserved for future use*.
CCF4
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
May generate a separate interrupt for this module alone.
CCF3
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
May generate a separate interrupt for this module alone.
CCF2
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
May generate a separate interrupt for this module alone.
CCF1
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
May generate a separate interrupt for this module alone.
CCF0
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
May generate a separate interrupt for this module alone.
Each of CCF4 through CCF0 generates its own interrupt, and has its own interrupt vector.
NOTE:
*
User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features. In that case, the reset or inactive value of the new bit will be
0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01307
76
5
4
3
210
Figure 11. CCON: PCA Counter Control Register
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