參數(shù)資料
型號(hào)： 935262650118
廠商： NXP SEMICONDUCTORS
元件分類： 總線收發(fā)器
英文描述： AHCT/VHCT SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20
封裝： 4.40 MM, PLASTIC, MO-153AC, SOT-360-1, TSSOP-20
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 97K
代理商： 935262650118
1999 Nov 23
2
Philips Semiconductors
Product specication
Octal D-type transparent latch; 3-state
74AHC373; 74AHCT373
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accepts voltages higher than VCC
Common 3-state output enable input
Functionally identical to the ‘533’, ‘563’ and ‘573’
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from 40 to +85 °C and 40 to +125 °C.
DESCRIPTION
The 74AHC/AHCT373 are high-speed Si-gate CMOS
devices and are pin compatible with Low power Schottky
TTL (LSTTL). They are specified in compliance with
JEDEC standard no. 7A.
The 74AHC/AHCT373 are octal D-type transparent
latches featuring separate D-type inputs for each latch and
3-state outputs for bus oriented applications. A Latch
Enable (LE) input and an Output Enable (OE) input are
common to all latches.
The ‘373’ consists of eight D-type transparent latches with
3-state true outputs. When LE is HIGH, data at the
Dn inputs enters the latches. In this condition the latches
are transparent, i.e. a latch output will change state each
time its corresponding D-input changes.
When LE is LOW the latches store the information that
was present at the D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the 8 latches are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance
OFF-state. Operation of the OE input does not affect the
state of the latches.
The ‘373’ is functionally identical to the ‘533’, ‘563’ and
‘573’, but the ‘533’ and ‘563’ have inverted outputs and the
‘563’ and ‘573’ have a different pin arrangement.
QUICK REFERENCE DATA
Ground = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
tPHL/tPLH
propagation delay
Dn to Qn; LE to Qn
CL = 15 pF; VCC = 5 V
4.3
ns
CI
input capacitance
VI =VCC or GND
3.0
pF
CO
output capacitance
4.0
pF
CPD
power dissipation
capacitance
CL = 50 pF; f = 1 MHz;
notes 1 and 2
10
12
pF
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