參數(shù)資料
型號(hào)： 935262680118
廠商： NXP SEMICONDUCTORS
元件分類： 總線收發(fā)器
英文描述： AHC SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20
封裝： 7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SO-20
文件頁(yè)數(shù)： 12/20頁(yè)
文件大小： 93K
代理商： 935262680118
1999 Sep 28
2
Philips Semiconductors
Product specication
Octal D-type ip-op; positive edge-trigger; 3-state
74AHC374;
74AHCT374
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger
actions
Inputs accepts voltages higher than
VCC
Common 3-state output enable
input
ICC category: MSI
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT374 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT374 are octal D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications.
A clock (CP) and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation
of the OE input does not affect the state of the flip-flops.
The ‘374’ is functionally identical to the ‘534’, but has non-inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
tPHL/tPLH
propagation delay;
CP to Qn
CL = 15 pF; VCC = 5 V
3.5
5.0
ns
fmax
maximum clock frequency
CL = 15 pF; VCC =5V
50
MHz
CI
input capacitance
VI =VCC or GND
3.0
pF
CO
output capacitance
4.0
pF
CPD
power dissipation
capacitance
CL = 50 pF; f = 1 MHz;
notes 1 and 2
10
12
pF
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