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參數(shù)資料
| 型號(hào)： | 935262682112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | AHCT/VHCT SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AC, SOT-163-1, SO-20 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 93K |
| 代理商： | 935262682112 |
1999 Sep 28
11
Philips Semiconductors
Product specication
Octal D-type ip-op; positive edge-trigger; 3-state
74AHC374;
74AHCT374
Type 74AHCT374
GND = 0 V; tr =tf ≤ 3.0 ns.
Note
1. Typical values at VCC = 5.0 V.
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb (°C)
UNIT
WAVEFORMS
CL
25
40 to +85
40 to +125
MIN.
TYP.
MAX.
MIN.
MAX.
MIN.
MAX.
VCC = 4.5 to 5.5 V; note 1
tPHL/tPLH
propagation delay
CP to Qn
see Figs 6, 8
and 9
15 pF
4.3
9.4
1.0
10.5
1.0
12.0
ns
tPZH/tPZL
propagation delay
OE to Qn
see Figs 7 and 9
3.5
10.2
1.0
11.5
1.0
13.0
ns
tPHZ/tPLZ
propagation delay
OE to Qn
3.6
10.2
1.0
11.0
1.0
13.0
ns
fmax
maximum clock
pulse frequency
see Figs 6 and 9
90
140
80
80
MHz
tPHL/tPLH
propagation delay
CP to Qn
see Figs 6, 8
and 9
50 pF
5.6
10.4
1.0
11.5
1.0
13.0
ns
tPZH/tPZL
propagation delay
OE to Qn
see Figs 7 and 9
4.8
11.2
1.0
12.5
1.0
14.0
ns
tPHZ/tPLZ
propagation delay
OE to Qn
5.7
11.2
1.0
12.0
1.0
14.0
ns
tW
clock pulse width
HIGH or LOW
see Figs 6 and 9
6.5
6.5
6.5
ns
tsu
set-up time
Dn to CP
see Figs 8 and 9
2.5
2.5
2.5
ns
th
hold time
Dn to CP
2.5
2.5
2.5
ns
fmax
maximum clock
pulse frequency
see Figs 6 and 9
85
130
75
75
MHz
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