參數(shù)資料
型號(hào)： 935262794557
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡(luò)
英文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： PLASTIC, SOT-317, QFP-100
文件頁(yè)數(shù)： 18/24頁(yè)
文件大?。?/td> 134K
代理商： 935262794557
2000 Feb 21
3
Philips Semiconductors
Product specication
Satellite demodulator and decoder
TDA8044
GENERAL DESCRIPTION
This document gives preliminary information about the
TDA8044 and TDA8044A, which are the successors of the
TDA8043. The TDA8044A is only specified where the
product deviates from the TDA8044, all other references
are the same. The TDA8044 is backwards compatible with
the TDA8043, with respect to pinning and the I2C-bus
software. The TDA8044 is a DVB compliant demodulator
and error correction decoder IC for reception of QPSK and
BPSK modulated signals for satellite applications. It can
handle variable symbol rates in the range of
0.5 to 45 Msymbols/s (0.5 to 30 Msymbols/s for
TDA8044A) with a minimum number of low cost and
non-critical external components. Typical applications for
this device are Multi Channel Per Carrier (MCPC), Single
Channel Per Carrier (SCPC) and simulcast. In these
applications one satellite transponder contains
respectively one broad QPSK carrier, several small QPSK
carriers and one small QPSK carrier together with one or
two FM carriers.
The TDA8044 has minimum interface with the tuner, it only
requires the demodulated analog I and Q baseband input
signals. Analog-to-digital conversion is performed
internally by two matched 7-bit ADCs. Since all the loops
(AGC, clock and carrier recovery) are internal, no
feedback to the tuner is needed. However, for maximum
tuner flexibility, there is the possibility to close the AGC
and carrier recovery loop externally via the tuner.
The number of external components required for operation
of the TDA8044 is very low. Moreover the external
components are low cost and non-critical. This gives an
easy and low cost application. The TDA8044 operates on
a low frequency crystal which is upconverted to a clock
frequency by means of an internal PLL. Different clock
frequencies can be selected with the PLL without changing
the crystal. This allows for maximum flexibility concerning
symbol rate range combined with minimum power
consumption.
The TDA8044 also has internal anti-alias filters, which can
cover a large range of symbol frequencies (approximately
one decade) without the need to switch external (SAW)
filters. To cover the whole range of 0.5 to 45 Msymbols/s
switching of clock frequency (internally) and filtering
(externally) is necessary.
The TDA8044 has a double carrier loop configuration
which has excellent capabilities of tracking phase noise.
Synchronization of the FEC unit is done completely
internally, thereby minimizing I2C-bus communication.
The output of the TDA8044 is highly flexible, allowing
different output modes to interface to a
demultiplexer/descrambler/MPEG-2 decoder including a
3-state mode. For evaluation of the TDA8044,
demodulator and Viterbi outputs can be made available
externally.
Interfacing to the TDA8044 has been extended compared
to the TDA8043. Separate resets are available for logic
only, logic plus I2C-bus and carrier loops. A Power-on
reset module has been implemented which gives a reset
signal at power-up. This signal can be used to reset the
TDA8044 in order to guarantee correct starting of the IC.
Two extra general purpose I/O pins (I/O expanders) have
been added. A switchable I2C-bus loop-through to the
tuner is implemented to switch-off the I2C-bus connection
to the tuner. This reduces phase noise in the tuner in the
event of I2C-bus crosstalk. The transport stream outputs
can be put in 3-state mode. DiSEqC level 1.X support is
integrated for dish control applications. The power
consumption in standby mode has been decreased
considerably.
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