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參數(shù)資料
| 型號(hào)： | 935262800118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 18 1-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | PLASTIC, SOT-364, TSSOP-56 |
| 文件頁(yè)數(shù)： | 2/22頁(yè) |
| 文件大小： | 135K |
| 代理商： | 935262800118 |
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1999 Oct 14
10
Philips Semiconductors
Product specication
18-bit universal bus transceiver with 30
termination resistor; 3-state
74ALVCH162601
AC CHARACTERISTICS FOR VCC = 2.3 TO 2.7 V
Ground = 0 V; tr =tf ≤ 2.0 ns; CL =30pF.
Note
1. All typical values are measured at Tamb =25 °C and VCC = 2.5 V.
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = 40 TO +85 °C
UNIT
WAVEFORMS
VCC (V)
MIN.
TYP.(1)
MAX.
tPHL/tPLH
propagation delay
An,Bn to Bn,An
see Figs 6 and 10
2.3 to 2.7 1.3
4.0
5.3
ns
propagation delay
LEAB,LEBA to Bn,An
see Figs 7 and 10
2.3 to 2.7
1.0
4.5
6.0
ns
propagation delay
CPAB,CPBA to Bn,An
see Figs 7 and 10
2.3 to 2.7
1.5
4.7
6.4
ns
tPZH/tPZL
3-state output enable time
OEAB, OEBA to Bn,An
see Figs 8 and 10
2.3 to 2.7
1.6
3.9
6.1
ns
tPHZ/tPLZ
3-state output disable time
OEAB, OEBA to Bn,An
see Figs 8 and 10
2.3 to 2.7
1.8
2.6
5.7
ns
tW
clock pulse width HIGH LEAB
or LEBA
see Figs 7 and 10
2.3 to 2.7
3.3
1.6
ns
clock pulse width HIGH or
LOW CPAB or CPBA
see Figs 7 and 10
2.3 to 2.7
3.3
2.0
ns
tsu
set-up time
An,Bn to CPAB,CPBA
see Figs 9 and 10
2.3 to 2.7
+2.3
0.2
ns
set-up time
An,Bn to LEAB,LEBA
see Figs 9 and 10
2.3 to 2.7
1.3
0.1
ns
set-up time
CEAB, CEBA to CPAB,CPBA
2.3 to 2.7
+2.0
0.4
ns
th
hold time
An,Bn to CPAB,CPBA
see Figs 9 and 10
2.3 to 2.7
1.2
0.3
ns
hold time
An,Bn to LEAB,LEBA
see Figs 9 and 10
2.3 to 2.7
1.3
0.2
ns
hold time
CEAB, CEBA to CPAB,CPBA
2.3 to 2.7
1.1
0.4
ns
fmax
maximum clock pulse
frequency
see Figs 7 and 10
2.3 to 2.7
150
190
MHz
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