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參數(shù)資料
| 型號： | 935263181026 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC56 |
| 封裝： | DIE |
| 文件頁數(shù)： | 4/43頁 |
| 文件大?。?/td> | 327K |
| 代理商： | 935263181026 |
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1997 Apr 01
12
Philips Semiconductors
Product specication
LCD column driver for dot matrix graphic
displays
PCF8579
7.3
Timing generator
The timing generator of the PCF8579 organizes the
internal data flow from the RAM to the display drivers.
An external synchronization pulse SYNC is received from
the PCF8578. This signal maintains the correct timing
relationship between cascaded devices.
7.4
Column drivers
Outputs C0 to C39 are column drivers which must be
connected to the LCD. Unused outputs should be left
open-circuit.
7.5
Display RAM
The PCF8579 contains a 32
× 40-bit static RAM which
stores the display data. The RAM is divided into 4 banks of
40 bytes (4
× 8 × 40 bits). During RAM access, data is
transferred to/from the RAM via the I2C-bus.
7.6
Data pointer
The addressing mechanism for the display RAM is
realized using the data pointer. This allows an individual
data byte or a series of data bytes to be written into, or read
from, the display RAM, controlled by commands sent on
the I2C-bus.
7.7
Subaddress counter
The storage and retrieval of display data is dependent on
the content of the subaddress counter. Storage and
retrieval take place only when the contents of the
subaddress counter agree with the hardware subaddress
at pins A0, A1, A2 and A3.
7.8
I2C-bus controller
The I2C-bus controller detects the I2C-bus protocol, slave
address, commands and display data bytes. It performs
the conversion of the data input (serial-to-parallel) and the
data output (parallel-to-serial). The PCF8579 acts as an
I2C-bus slave transmitter/receiver. Device selection
depends on the I2C-bus slave address, the hardware
subaddress and the commands transmitted.
7.9
Input lters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.10
RAM access
There are three RAM ACCESS modes:
Character
Half-graphic
Full-graphic.
These modes are specified by bits G1 and G0 of the RAM
ACCESS command. The RAM ACCESS command
controls the order in which data is written to or read from
the RAM (see Fig.8).
To store RAM data, the user specifies the location into
which the first byte will be loaded (see Fig.9):
Device subaddress (specified by the DEVICE SELECT
command)
RAM X-address (specified by the LOAD X-ADDRESS
command)
RAM bank (specified by bits Y1 and Y0 of the RAM
ACCESS command).
Subsequent data bytes will be written or read according to
the chosen RAM access mode. Device subaddresses are
automatically incremented between devices until the last
device is reached. If the last device has subaddress 15,
further display data transfers will lead to a wrap-around of
the subaddress to 0.
7.11
Display control
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The number of rows scanned depends on the multiplex
rate set by bits M1 and M0 of the SET MODE command.
The display status (all dots on/off and normal/inverse
video) is set by bits E1 and E0 of the SET MODE
command. For bank switching, the RAM bank
corresponding to the top of the display is set by bits
B1 and B0 of the SET START BANK command. This is
shown in Fig.10 This feature is useful when scrolling in
alphanumeric applications.
7.12
TEST pin
The TEST pin must be connected to VSS.
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