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參數(shù)資料
| 型號： | 935263208557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, QFP-80 |
| 文件頁數(shù)： | 59/76頁 |
| 文件大小： | 567K |
| 代理商： | 935263208557 |
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Philips Semiconductors
Product specification
P83C557E4/P80C557E4/P89C557E4
Single-chip 8-bit microcontroller
1999 Mar 02
62
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1.
See Figures 55 and 57 through 59 for IDD test conditions.
2.
The operating supply current is measured with all output pins disconnected;
XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5 V; VIH = VDD – 0.5 V; XTAL2, XTAL3 not connected;
EA = RSTIN = Port 0 = EW = SCL = SDA = SELXTAL1 = VDD; ADEXS = XTAL4 = VSS.
3.
The Idle Mode supply current is measured with all output pins disconnected;
XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5 V; VIH = VDD – 0.5 V; XTAL2, XTAL3 not connected;
Port 0 = EW = SCL = SDA = SELXTAL 1 = VDD; EA = RSTIN = ADEXS = XTAL4 = VSS.
4.
The Power-down current is measured with all output pins disconnected;
XTAL2 not connected; Port 0 = EW = SCL = SDA = SELXTAL 1 = VDD; EA = RSTIN = ADEXS = XTAL1 = XTAL4 = VSS.
5.
The input threshold voltage of SCL and SDA (SIO1) meets the I2C specification, so an input voltage below 0.3 VDD will be recognized as a
logic 0 while an input voltage above 0.7 VDD will be recognized as a logic 1.
6.
Pins of ports 1, 2, 3, and 4 source a transition current when they are being externally driven from HIGH to LOW. The transition current reaches
its maximum value when VIN is approximately 2 V.
7.
Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL of ALE and ports 1, 3 and 4. The noise is
due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations.
In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to
qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
8.
Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the address
bits are stabilizing.
9.
Conditions: AVREF– = 0 V; AVDD = 5.0 V, AVREF+ = 5.12 V. VDD = 5.0 V, VSS = 0 V, ADC is monotonic with no missing codes. Measurement
by continuous conversion of AVIN = –20mV to 5.12 V in steps of 0.5mV, derivating parameters from collected conversion results of ADC.
ADC prescaler programmed according to the actual oscillator frequency, resulting in a conversion time within the specified range for tconv
(15
s ... 50s).
10. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width.
11. The ADC is monotonic; there are no missing codes.
12. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset error.
13. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
a straight line which fits the ideal transfer curve. The offset error is constant at every point of the actual transfer curve.
14. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve.
15. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve.
16. This should be considered when both analog and digital signals are simultaneously input to port 5.
17. The supply current with 32 kHz oscillator running and PLL operation (SELXTAL1 = 0) is measured with all output pins disconnected;
XTAL4 driven with tr = tf = 5ns; VIL = VSS + 0.5 V; VIH = VDD – 0.5 V; XTAL2 not connected;
Port 0 = EW = SCL = SDA = VDD; EA = RSTIN = ADEXS = SELXTAL 1 = XTAL1 = VSS.
18. Not 100% tested; sum of AIID (PLL) and AIDD (HF-Oscillator).
19. The parameter meets the I2C bus specification for standard-mode and fast-mode devices.
20. Not 100% tested.
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