參數(shù)資料
型號(hào)： 935263263557
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, QFP-80
文件頁(yè)數(shù)： 14/76頁(yè)
文件大?。?/td> 567K
代理商： 935263263557
Philips Semiconductors
Product specification
P83C557E4/P80C557E4/P89C557E4
Single-chip 8-bit microcontroller
1999 Mar 02
21
6.6.2
Configuration and Operation
Every A/D conversion is an autoscan conversion. The two user
selectable general operation modes are continuous scan and
one-time scan mode.
The desired analog input port channel/s for conversion is/are
selected by programming A/D input port scan-select bits in SFR
ADPSS. An analog input channel is included in the autoscan loop if
the corresponding bit in ADPSS is 1, a channel is skipped if the
corresponding bit in ADPSS is 0.
An autoscan is always started according to the lowest bit position of
ADPSS that contains a 1.
An autoscan conversion is started by setting the flag ADSST in
register ADCON either by software or by an external start signal at
input pin ADEXS, if enabled. Either no edge (external start totally
disabled), a rising edge or/and a falling edge of ADEXS is selectable
for external conversion start by the bits ADSRE and ADSFE in
register ADCON.
After completion of an A/D conversion the 10-bit result is stored in
the corresponding 10-bit buffer register. Then the next analog input
is selected according to the next higher set bit position in ADPSS,
converted and stored, and so on. When the result of the last
conversion of this autoscan loop is stored, flag ADCON.4/ADINT,
the ADC interrupt flag, is set. It is not cleared by interrupt hardware
– it must be cleared by software.
In continuous scan mode (ADCON.2/ADCSA=1) the ADC start and
status flag ADCON.3/ADSST retains the set state and the autoscan
loop restarts from the beginning. In one-time scan mode (ADCSA=0)
conversions stop after the last selected analog input was converted,
ADINT is set and ADSST is cleared automatically.
ADSST cannot be set (neither externally nor by software) as long as
ADINT=1, i.e. as long as ADINT is set, a new conversion start – by
setting flag ADSST – is inhibited; actually it is only delayed until
ADINT is cleared.
(If a ‘1’ is written to ADSST while ADINT=1, this new value is
internally latched and preserved, not setting ADSST until
ADCON.4/ADINT=0. In this state, a read of SFR ADCON will display
ADCON.3/ADSST=0, because always the effective ADC status is
read.)
Note that under software control the analog inputs can also be
converted in arbitrary order, when one-time scan mode is selected
and in SFR ADPSS only one bit is set at a time. In this case ADINT
is set and ADSST is cleared after every conversion.
6.6.3
Resolution and Characteristics
The ADC system has its own analog supply pins AVDD and AVSS. It
is referenced by two special reference voltage input pins sourcing
the resistance ladder of the DAC: AVref+ and AVref–. The voltage
between AVREF+ and AVREF– defines the full-scale range. Due to
the 10-bit resolution the full scale range is divided into 1024 unit
steps. The unit step voltage is 1 LSB, which is typically 5 mV
(AVref+ = 5.12 V, AVref– = 0 V = AVSS).
The DAC’s resistance ladder has 1023 equally spaced taps,
separated by a unit resistance ’R’. The first tap is located 0.5 x R
above AVref–, the last tap is located 1.5 x R below AVref+. This
results in a total ladder resistance of 1024 x R. This structure
ensures that the DAC is monotonic and results in a symmetrical
quantization error. For input voltages between AVref– and
(AVref– + 1/2 LSB) the 10-bit conversion result code will be
00 0000 0000 B = 000H = 0D. For input voltages between
(AVref+ – 3/2 LSB) and AVref+ the 10-bit conversion result code will
be 11 1111 1111 B = 3FFH = 1023D.
The result code corresponding to an analog input voltage (AVin) can
be calculated from the formula:
ResultCode
+ 1024
AV
IN * AVref
*
AV
ref
) * AVref*
The analog input voltage should be stable when it is sampled for
conversion. At any times the input voltage slew rate must be less
than 10 V/ms (5 V conversion range) in order to prevent an
undefined result.
This maximum input voltage slew rate can be ensured by an RC low
pass filter with R = 2k2 and C = 100 nF. The capacitor between
analog input pin and analog ground pin shall be placed close to the
pins in order to have maximum effect in minimizing input noise
coupling.
6.7
Timer/Counters
The P8xC557E4 contains three 16-bit timer/event counters: Timer 0,
Timer 1 and Timer T2 and one 8-bit timer, T3. Timer 0 and Timer 1
may be programmed to carry out the following functions:
Measure time intervals and pulse durations
Count events
Generate interrupt requests
6.7.1
Timer 0 and Timer 1
Timers 0 and 1 each have a control bit in SFR TMOD that selects
the timer or counter function of the corresponding timer.
In the timer function, the register is incremented every machine
cycle. Thus, one can think of it as counting machine cycles. Since a
machine cycle consists of 12 oscillator periods, the count rate is
1/12 of the oscillator frequency.
In the counter function, the register is incremented in response to a
1-to-0 transition at the corresponding external input pin, T0 or T1. In
this function, the external input is sampled during S5P2 of every
machine cycle. When the samples show a HIGH in one cycle and a
LOW in the next cycle, the counter is incremented. Thus, it takes
two machine cycles (24 oscillator periods) to recognize a 1-to-0
transition. There are no restrictions on the duty cycle of the external
input signal, but to insure that a given level is sampled at least once
before it changes, it should be held for at least one full machine
cycle.
Timer 0 and Timer 1 can be programmed independently to operate
in one of four modes:
Mode 0:
8-bit timer or 8-bit counter each with divide-by-32 prescaler
Mode 1:
16-bit time-interval or event counter
Mode 2:
8-bit time-interval or event counter with automatic reload
upon overflow
Mode 3:
–Timer 0: one 8-bit time-interval or event counter and
one 8-bit time-interval counter
–Timer 1: stopped
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