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    參數(shù)資料
    型號(hào)： 935263292112
    廠商： NXP SEMICONDUCTORS
    元件分類： 微控制器/微處理器
    英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
    封裝： PLASTIC, LCC-44
    文件頁(yè)數(shù)： 53/80頁(yè)
    文件大?。?/td> 446K
    代理商： 935263292112
    1997 Dec 15
    57
    Philips Semiconductors
    Product specication
    8-bit microcontrollers
    P83C524; P80C528; P83C528
    21.2
    AC Characteristics 24 MHz version
    See notes 1, 2 and 3.; Cl = 100 pF for Port 0, ALE and PSEN; CL = 80 pF for all other outputs unless otherwise
    specied.
    Notes to the AC Characteristics 16 and 24 MHz versions
    1. For the AC Characteristics the following conditions are valid:
    a) P83C52x EBx: VDD =5 V ±10%; VSS =0 V; Tamb = 0 to +70 °C; tCK min.=63ns
    b) P83C52x EFx: VDD =5V ±10%; VSS =0V; Tamb = 40 to +85 °C; tCK min. = 63 ns.
    2. tCK min. = 1/f max. (maximum operating frequency); tCK = clock period (see section for timing symbol denitions).
    3. The maximum operating frequency is limited to 16/24 MHz and the minimum to 3.5 MHz (all versions Ixx/Exx).
    SYMBOL
    PARAMETER
    24 MHZ
    VARIABLE CLOCK
    UNIT
    MIN.
    MAX.
    MIN.
    MAX.
    External program memory
    tLHLL
    ALE pulse duration
    43
    2 tCK40
    ns
    tAVLL
    address set-up time to ALE
    17
    tCK25
    ns
    tLLAX
    address hold time after ALE
    17
    tCK25
    ns
    tLLIV
    time from ALE to valid instruction input
    102
    4 tCK65
    ns
    tLLPL
    time from ALE to control pulse PSEN
    17
    tCK25
    ns
    tPLPH
    control pulse duration PSEN
    80
    3 tCK45
    ns
    tPLIV
    time from PSEN to valid instruction input
    65
    3 tCK60
    ns
    tPXIX
    input instruction hold time after PSEN
    0
    0
    ns
    tPXIZ
    input instruction oat delay after PSEN
    17
    tCK25
    ns
    tAVIV
    address to valid instruction input
    128
    5 tCK80
    ns
    tPLAZ
    address oat time to PSEN
    10
    10
    ns
    External data memory
    tLHLL
    ALE pulse duration
    43
    2 tCK40
    ns
    tAVLL
    address set-up time to ALE
    17
    tCK25
    ns
    tLLAX
    address hold time after ALE
    17
    tCK25
    ns
    tRLRH
    RD pulse duration
    150
    6 tCK100
    ns
    tWLWH
    WR pulse duration
    150
    6 tCK100
    ns
    tRLDV
    RD to valid data input
    118
    5 tCK90
    ns
    tRHDX
    data hold time after RD
    0
    0
    ns
    tRHDZ
    data oat delay after RD
    55
    2 tCK28
    ns
    tLLDZ
    time from ALE to valid data input
    183
    8 tCK150
    ns
    tAVDV
    address to valid data input
    210
    9 tCK165
    ns
    tLLWL
    time from ALE to RD or WR
    75
    175
    3 tCK50
    3 tCK+50
    ns
    tAVWL
    time from address to RD or WR
    92
    4 tCK75
    ns
    tWHLH
    time from RD or WR HIGH to ALE HIGH
    17
    67
    tCK25
    tCK+ 25
    ns
    tQVWX
    data valid to WR transition
    12
    tCK30
    ns
    tQVWH
    data set-up time before WR
    162
    7 tCK130
    ns
    tWHQX
    data hold time after WR
    17
    tCK25
    ns
    tRLAZ
    address oat delay after RD
    0
    0ns
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