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參數(shù)資料
| 型號： | 935263512112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 多路復(fù)用及模擬開關(guān) |
| 英文描述： | TRIPLE 2-CHANNEL, SGL ENDED MULTIPLEXER, PDSO16 |
| 封裝： | PLASTIC, SOT-109, SO-16 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 115K |
| 代理商： | 935263512112 |
January 1995
3
Philips Semiconductors
Product specication
Triple 2-channel analogue
multiplexer/demultiplexer
HEF4053B
MSI
HEF4053BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4053BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4053BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
PINNING
FUNCTION TABLE
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
Y0A to Y0C
independent inputs/outputs
Y1A to Y1C
independent inputs/outputs
SA to SC
select inputs
E
enable input (active LOW)
ZA to ZC
common inputs/outputs
INPUTS
CHANNEL
ON
ESn
LL
Y0nZn
LH
Y1nZn
H
X
none
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Note
1. To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across
the bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no VDD current will flow out
of terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may
not exceed VDD or VEE.
Supply voltage (with reference to VDD)VEE
18 to + 0,5 V
Fig.3 Schematic diagram (one switch).
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