2000 Jul 03
2
Philips Semiconductors
Product specication
10-bit high-speed low-power ADC
TDA8764A
FEATURES
10-bit resolution (binary or gray code)
Sampling rate up to 60 MHz
DC sampling allowed
One clock cycle conversion only
High signal-to-noise ratio over a large analog input
frequency range (9.3 effective bits at 5 MHz full-scale
input at fclk = 60 MHz)
No missing codes guaranteed
In Range (IR) CMOS output
TTL and CMOS levels compatible digital inputs
2.7 to 3.6 V CMOS digital outputs
Low-level AC clock input signal allowed
Power dissipation only 312 mW
Low analog input capacitance, no buffer amplifier
required
No sample-and-hold circuit required.
APPLICATIONS
High-speed analog-to-digital conversion for:
Video data digitizing
Radar pulse analysis
High energy physics research
Transient signal analysis
Σ modulators
Medical imaging.
GENERAL DESCRIPTION
The TDA8764A is a 10-bit high-speed low-power
Analog-to-Digital Converter (ADC) for professional video
and other applications. It converts the analog input signal
into 10-bit binary or gray coded digital words at a maximum
sampling rate of 60 MHz. All digital inputs and outputs are
TTL and CMOS compatible, although a low-level sine
wave clock input signal is allowed.
The device requires an external source to drive its
reference ladder.
ORDERING INFORMATION
QUICK REFERENCE DATA
TYPE NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA8764ATS/6
SSOP28
plastic shrink small outline package; 28 leads; body width 5.3 mm
SOT341-1
TDA8764AHL/6
LQFP32
plastic low prole quad at package; 32 leads; body 5
× 5 × 1.4 mm
SOT401-1
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VCCA
analog supply voltage
4.75
5.0
5.25
V
VCCD
digital supply voltage
4.75
5.0
5.25
V
VCCO
output stages supply voltage
2.7
3.3
3.6
V
ICCA
analog supply current
29
37
mA
ICCD
digital supply current
33
40
mA
ICCO
output stages supply current
fclk = 60 MHz; ramp input
0.5
2.0
mA
INL
integral non-linearity
fclk = 60 MHz; ramp input ±0.8
±2
LSB
DNL
differential non-linearity
fclk = 60 MHz; ramp input ±0.35
±0.9
LSB
fclk(max)
maximum clock frequency
TDA8764ATS and
TDA8764AHL
60
MHz
Ptot
total power dissipation
fclk = 60 MHz; ramp input
312
411
mW