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參數資料
| 型號： | 935264253118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復用、解復用 |
| 英文描述： | CBT/FST/QS/5C/B SERIES, 12 1 LINE TO 2 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, PLASTIC, MO-153EE, SOT-364-1, TSSOP-56 |
| 文件頁數： | 5/8頁 |
| 文件大?。?/td> | 56K |
| 代理商： | 935264253118 |
Philips Semiconductors
Product specification
CBT16292
12-bit 1-of-2 multiplexer/demultiplexer
with internal pulldown resistors
1999 Sep 13
5
AC CHARACTERISTICS
GND = 0 V; tR = tf ≤ 2.5 ns; CL = 50 pF
SYMBOL
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC = 5.0V ±0.5V
UNIT
SYMBOL
PARAMETER
FROM (INPUT)
TO (OUTPUT)
Min
Max
UNIT
tpd
Propagation delay1
A or B
B or A
0.4
ns
ten
Output enable time
to High and Low level
S
A or B
1.5
5.8
ns
tdis
Output disable time
from High and Low level
S
A or B
1.5
4.5
ns
tbbm2
Break-before-make time
A
nB1 or nB2
0
2
ns
NOTE:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
2. Time interval between break and make measured at the same operating point (VCC and temperature).
AC WAVEFORMS
VM = 1.5 V, VIN = GND to 3.0 V
INPUT
1.5V
OUTPUT
tPLH
tPHL
SA00028
1.5V
3 V
0 V
VOH
VOL
Waveform 1. Input (An) to Output (Yn) Propagation Delays
Output Control
(Low-level
enabling
1.2 V
tPZH
tPHZ
VOH
VOL
tPZL
tPLZ
2.3V
0V
VOL + 0.3V
VOH – 0.3V
1.2 V
1.5 V
0V
3V
Output
Waveform 1
S1 at 7 V
(see Note)
Note:
Waveform 1 is for an output with internal conditions such that
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is high except when disabled by the output control.
Output
Waveform 2
S1 at Open
(see Note)
SA00530
Waveform 2. 3-State Output Enable and Disable Times
TEST CIRCUIT AND WAVEFORMS
CL = 50 pF
500
Load Circuit
DEFINITIONS
CL =
Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
TEST
S1
tpd
open
tPLZ/tPZL
7 V
tPHZ/tPZH
open
SA00012
500
From Output
Under Test
S1
7 V
Open
GND
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