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參數(shù)資料
| 型號(hào)： | 935264405118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-355-1, TSSOP-24 |
| 文件頁(yè)數(shù)： | 4/10頁(yè) |
| 文件大?。?/td> | 95K |
| 代理商： | 935264405118 |
Philips Semiconductors
Product specification
PCK2510S
50–150 MHz 1:10 SDRAM clock driver
2001 Feb 02
3
PIN DESCRIPTIONS
PIN NUMBER
SYMBOL
TYPE
NAME, FUNCTION, and DIRECTION
1
AGND
GND
Analog ground. AGND provides the ground reference for the analog circuitry.
2, 10, 14, 22
VCC
PWR
Power supply
3, 4, 5, 8, 9,
15, 16, 17, 20, 21
1Y (0–9)
OUT
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y (0–9) is enabled
via the G input. These outputs can be disabled to a logic-low state by de-asserting the G control
input. Each output has an integrated 25
series-damping resistor.
6, 7, 18, 19
GND
Ground
11
G
IN
Output bank enable. G is the output enable for outputs 1Y (0–9). When G is LOW, outputs 1Y
(0–9) are disabled to a logic LOW state. When G is HIGH, all outputs 1Y (0–9) are enabled and
switch at the same frequency as CLK.
12
FBOUT
OUT
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency
as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.
FBOUT has an integrated 25
series-damping resistor.
13
FBIN
IN
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be
hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so
that there is nominally zero phase error between CLK and FBIN.
23
AVCC
PWR
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition,
AVCC can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL
is bypassed and CLK is buffered directly to the device outputs.
24
CLK
IN
Clock input. CLK provides the clock signal to be distributed by the PCK2510S clock driver. CLK
is used to provide the reference signal to the integrated PLL that generates the clock output
signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock.
Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required
for the PLL to phase lock the feedback signal to its reference signal.
FUNCTION TABLE
INPUTS
OUTPUTS
G
CLK
1Y (0–9)
FBOUT
X
L
H
L
H
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