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參數(shù)資料
| 型號： | 935265483112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | AVC SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362, TSSOP-48 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 87K |
| 代理商： | 935265483112 |
2000 Mar 09
3
Philips Semiconductors
Product Specication
16-bit D-type transparent latch; 3.6 V tolerant;
3-state
74AVC16373
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
2. The condition is VI = GND to VCC.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high impedance OFF-state.
SYMBOL
PARAMETER
CONDITIONS
TYP.
UNIT
tPHL/tPLH
propagation delay
nDn to nQn
VCC = 1.2 V
3.6
ns
VCC = 1.5 V
3.1
ns
VCC = 1.8 V
2.2
ns
VCC = 2.5 V
1.6
ns
VCC = 3.3 V
1.4
ns
CI
input capacitance
5.0
pF
CPD
power dissipation
capacitance per buffer
notes 1 and 2
outputs enabled
34
pF
outputs disabled
1
pF
OPERATING MODES
INPUTS
INTERNAL
LATCHES
OUTPUTS
nOE
LE
nAn
nYn
Enable and read register
(transparent mode)
L
H
L
H
L
H
L
H
Latch and read register
(hold mode)
L
l
h
L
H
L
H
Latch register and disable outputs
H
L
l
h
L
H
Z
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| 935265484112 | AVC SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48 |
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| 08-50-0183 | Crimp Socket Contact; Wire Size (AWG):26-22; Contact Material:Brass |
| 08-50-0185 | Solderless Terminal; Body Material:Brass; Contact Plating:Tin; Series:7258; Wire Size (AWG):26-22; External Depth:0.065"; Lead Pitch:3.96mm; Operating Temp. Min:0 C; Voltage Rating:250V RoHS Compliant: Yes |
| 08-52-0124 | Crimp Socket Contact; Wire Size (AWG):26-22; Contact Material:Phosphor Bronze; Contact Plating:Tin |
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