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參數(shù)資料
| 型號： | 935265567112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計數(shù)移位寄存器 |
| 英文描述： | AHC SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-109-1, SO-16 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 103K |
| 代理商： | 935265567112 |
2000 Mar 15
14
Philips Semiconductors
Product specication
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
handbook, full pagewidth
MNA560
GND
th
tsu
th
tsu
VM
(1)
VM
(1)
VM
(2)
VI
VOH
VOL
VI
Q7' output
SHCP input
DS input
Fig.9 The data set-up (tsu) and hold (th) times for the DS input.
FAMILY
VI INPUT
REQUIREMENTS
VM(1)
INPUT
VM(2)
OUTPUT
AHC
GND to VCC
50% VCC 50% VCC
AHCT
GND to 3.0 V
1.5 V
50% VCC
The shaded areas indicate when the input is permitted to change for
predictable output performance.
handbook, full pagewidth
MNA561
MR input
SHCP input
Q7' output
tPHL
tW
trem
VM
(2)
VOH
VOL
VI
GND
VI
GND
VM
(1)
VM
(1)
FAMILY
VI INPUT
REQUIREMENTS
VM(1)
INPUT
VM(2)
OUTPUT
AHC
GND to VCC
50% VCC 50% VCC
AHCT
GND to 3.0 V
1.5 V
50% VCC
Fig.10 The master reset (MR) pulse width, the master reset to output (Q7’) propagation delays and the master
reset to shift clock (SHCP) removal time (trem).
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