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參數(shù)資料
| 型號： | 935265568112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | AHC SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 103K |
| 代理商： | 935265568112 |
2000 Mar 15
10
Philips Semiconductors
Product specication
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74AHC595; 74AHCT595
AC CHARACTERISTICS
Type 74AHC595
GND = 0 V; tr =tf ≤ 3.0 ns.
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb (°C)
UNIT
WAVEFORMS
CL
25
40 to +85
40 to +125
MIN.
TYP.
MAX.
MIN.
MAX.
MIN.
MAX.
VCC = 3.0 to 3.6 V; note 1
tPHL/tPLH
propagation delay
SHCP to Q7’
see Figs 7
and 12
15 pF
5.7
13.0
1.0
15.0
1.0
16.5
ns
propagation delay
STCP to Qn
see Figs 8
and 12
5.9
11.9
1.0
13.5
1.0
15.0
ns
tPHL
propagation delay
MR to Q7’
see Figs 10
and 12
5.9
12.8
1.0
13.7
1.0
15.0
ns
tPZH/tPZL
3-state output enable
time OE to Qn
see Figs 11
and 12
5.6
11.5
1.0
13.5
1.0
15.0
ns
tPHZ/tPLZ
3-state output disable
time OE to Qn
5.4
11.0
1.0
13.0
1.0
14.5
ns
tPHL/tPLH
propagation delay
SHCP to Q7’
see Figs 7
and 12
50 pF
7.7
16.5
1.0
18.5
1.0
20.1
ns
propagation delay
STCP to Qn
see Figs 8
and 12
7.7
15.4
1.0
17.0
1.0
18.5
ns
tPHL
propagation delay
MR to Q7’
see Figs 10
and 12
7.4
16.3
1.0
17.2
1.0
18.7
ns
tPZH/tPZL
3-state output enable
time OE to Qn
see Figs 11
and 12
7.4
15.0
1.0
17.0
1.0
18.5
ns
tPHZ/tPLZ
3-state output disable
time OE to Qn
8.7
15.7
1.0
16.2
1.0
17.5
ns
tW
shift clock pulse width
HIGH or LOW
see Figs 7
and 12
5.0
5.0
5.0
ns
storage clock pulse
width HIGH or LOW
see Figs 8
and 12
5.0
5.0
5.0
ns
master reset pulse
width LOW
see Figs 10
and 12
5.0
5.0
5.0
ns
tsu
set-up time
DS to SHCP
see Figs 8
and 12
3.5
3.5
3.5
ns
set-up time
SHCP to STCP
see Figs 9
and 12
8.5
8.5
8.5
ns
th
hold time
DS to SHCP
1.5
1.5
1.5
ns
trem
removal time
MR to SHCP
see Figs 10
and 12
3.0
3.0
3.0
ns
fmax
maximum clock pulse
frequency
SHCP or STCP
see Figs 7, 8
and 12
80
125
60
40
MHz
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