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參數(shù)資料
| 型號： | 935266896551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP100 |
| 封裝： | PLASTIC, SOT-317-2, QFP-64 |
| 文件頁數(shù)： | 20/40頁 |
| 文件大小： | 250K |
| 代理商： | 935266896551 |
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1999 Feb 24
27
Philips Semiconductors
Product specication
Triple high-speed Analog-to-Digital
Converter (ADC)
TDA8752A
Notes
1. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST
frequency). Conversion-to-noise ratio: S/N = EB
× 6.02 + 1.76 dB.
2. Output data acquisition is available after the maximum delay time td(o), which is the time during which the data is
available. All the timings are given for a 10 pF capacitive load. A higher load can be used but the timing must then
be rechecked.
3. The I2C-bus timings are given for a frequency of 100 kbit/s (100 kHz). This bus can be used at a frequency of
400 kbit/s (400 kHz).
I2C-bus; see note 3
fSCL
clock frequency
0
100
kHz
tBUF
time the bus must be free
before new transmission can
start
4.7
s
tHD;STA
start condition hold time
4.0
s
tSU;STA
start condition set-up time
repeated start
4.7
s
tCKL
LOW-level clock period
4.7
s
tCKH
HIGH-level clock period
4.0
s
tSU;DAT
data set-up time
250
ns
tHD;DAT
data hold time
0
ns
tr
SDA and SCL rise time
for fSCL = 100 kHz
1.0
s
tf
SDA and SCL fall time
for fSCL = 100 kHz
300
ns
tSU;STOP
stop condition set-up time
4.0
s
CL(bus)
capacitive load for each bus
line
400
pF
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fig.11 Timing diagram.
handbook, full pagewidth
td(s)
sample N
+ 1
sample N
CKADCO
n
MGL103
sample N
+ 2
50 % = 1.4 V
1.4 V
2.4 V
0.4 V
VlN
DATA
R0 to R7, ROR
G0 to G7, GOR
B0 to B7, BOR
td(o)
th(o)
tCPH
tCPL
In + 2
In + 1
In
In 1
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