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參數(shù)資料
| 型號： | 935267384118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, 16 1-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 121K |
| 代理商： | 935267384118 |
Philips Semiconductors
Product specification
74ALVC16334A
16-bit registered driver with inverted register enable
(3-State)
2
2000 Mar 14
853–2196 23314
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTETM flow-through standard pin-out architecture
Low inductance multiple V
CC and GND pins for minimum noise
and ground bounce
Output drive capability 50 transmission lines @ 85°C
Input diodes to accommodate strong drivers
DESCRIPTION
The 74ALVC16334A is a 16–bit universal bus driver. Data flow is
controlled by active low output enable (OE), active low latch enable
(LE) and clock inputs (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is
HIGH and CP is held at LOW or HIGH, the data is latched; on the
LOW to HIGH transient of CP the A-data is stored in the
latch/flip-flop.
When OE is LOW the outputs are active. When OE is HIGH, the
outputs go to the high impedance OFF-state. Operation of the OE
input does not affect the state of the latch/flip-flop.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
OE
Y1
Y2
Y3
Y4
Y5
GND
VCC
GND
Y6
Y7
Y8
Y9
Y10
Y11
GND
Y12
Y13
Y14
Y15
Y16
GND
CP
GND
A1
A2
A3
A4
VCC
A5
GND
A6
A7
A8
A9
A10
A11
GND
A12
A13
A14
VCC
A15
A16
GND
LE
SH00198
VCC
NC
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
An to Yn;
LE to Yn;
CP to Yn
VCC = 3.3 V, CL = 50 pF
2.3
2.6
2.5
ns
Fmax
Maximum clock frequency
VCC = 3.3 V, CL = 50 pF
350
MHz
CI
Input capacitance
4.0
pF
CI/O
Input/Output capacitance
8.0
pF
C
Power dissipation capacitance per buffer
V = GND to VCC1
transparent mode
Output enabled
Output disabled
13
3
pF
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
Clocked mode
Output enabled
Output disabled
22
15
pF
NOTE:
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
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